CVSROOT: /cvs
Module name: src
Changes by: j...@cvs.openbsd.org 2019/12/20 00:55:30
Modified files:
sys/arch/i386/i386: acpi_machdep.c cpu.c
sys/arch/i386/include: cpu.h specialreg.h
Log message:
Disable TSX when MSR_ARCH_CAPABILITIES sets TSX_CTRL.
Even with the latest microcode this is not set on all CPUs with TSX, but
is set on CPUs which don't need MDS mitigations.
MDS mitigations also mitigate TSX Asynchronous Abort (TAA) but aren't
done if the CPU claims to not be affected by MDS (MDS_NO).
According to "Deep Dive: Intel Transactional Synchronization Extensions
(Intel TSX) Asynchronous Abort" CPUs requiring additional mitigations
for this are:
06-8e-0c Whiskey Lake (ULT refresh)
06-55-0{6,7} 2nd Gen Xeon Scalable Processors based on Cascade Lake
06-9e-0d Coffee Lake R
Currently TSX is disabled unconditionally when possible even if TAA_NO
is set.
We don't currently do MDS mitigations on i386. Attempt to disable TSX
regardless to match amd64.
