CVSROOT: /cvs
Module name: src
Changes by: u...@cvs.openbsd.org 2020/08/29 23:23:49
Modified files:
sys/dev/fdt : sxiccmu.c
Log message:
PLL1(CPU_PLL) stability improvement for Allwinner H3/H2+
Due to unstable of PLL1, sometimes the system has hanged up
especially at boot. This is observed at Allwinner H3/H2+ processor.
To solve the problem, PLL1 setting procedure is same as Linux.
1. change clock source to 24MHz
2. wait 1usec (new)
3. disable PLL1 (new)
4. set new NKMP value, but M should be 1
5. re-enable PLL1 (new)
6. wait PLL1 stable (modified)
7. change clock source to PLL1
8. wait 1usec (new)
Once disable PLL1 before setting NKMP is very important. And, sometimes
LOCK flag is set even if PLL has not locked yet so wait for PLL is
modified with simple delay() by the value of PLL_STABLE_TIME_REG1 register.
Not only Allwinner H3/H2+ but also all (i.e. A64) Allwinner processors
datasheet has "If the clock source is changed, at most to wait for 8
present running clock cycles." sentence at CPU clock source selection
field of CPU/AXI configuration register. But this is ambiguous that
_who_ should do _what_ during that cycles.
It is unclear that changing clock source itself invoke PLL1 unstability.
For safety, added 1usec wait after changing clock source like Linux.
ok by kettenis@, thanks to adr at sdf dot org
