CVSROOT: /cvs
Module name: src
Changes by: [email protected] 2009/10/22 16:08:54
Modified files:
sys/arch/mips64/include: cpu.h cpustate.h frame.h trap.h
sys/arch/mips64/mips64: clock.c context.S exception.S
interrupt.c process_machdep.c softintr.c
vm_machdep.c
sys/arch/sgi/include: intr.h mutex.h
sys/arch/sgi/localbus: crimebus.h macebus.c
sys/arch/sgi/sgi: genassym.cf ip27_machdep.c ip30_machdep.c
mutex.c
sys/arch/sgi/xbow: hub.h xbridge.c xheart.c xheartreg.h
Added files:
sys/arch/sgi/sgi: intr_template.c
Log message:
Completely overhaul interrupt handling on sgi. Cpu state now only stores a
logical IPL level, and per-platform (IP27/IP30/IP32) code will from the
necessary hardware mask registers.
This allows the use of more than one interrupt mask register. Also, the
generic (platform independent) interrupt code shrinks a lot, and the actual
interrupt handler chains and masking information is now per-platform private
data.
Interrupt dispatching is generated from a template; more routines will be
added to the template to reduce platform-specific changes and share as much
code as possible.
Tested on IP27, IP30, IP32 and IP35.
