CVSROOT: /cvs Module name: src Changes by: [email protected] 2021/05/19 11:39:50
Modified files:
sys/arch/riscv64/dev: plic.c
sys/arch/riscv64/include: fdt.h intr.h
sys/arch/riscv64/riscv64: intr.c
Log message:
Bring riscv64 intr.c code in sync with arm64. This brings us:
- MSI support
- Interfaces to route interrupts to specific CPUs
- Proper interrupt barriers
- s/riscv_intr_handler/machine_intr_handler/
ok mlarkin@
