CVSROOT: /cvs
Module name: src
Changes by: j...@cvs.openbsd.org 2021/06/10 23:33:16
Modified files:
sys/arch/amd64/amd64: lapic.c
sys/arch/i386/i386: lapic.c
Log message:
limit workaround for AMD errata 400 to family 0fh and 10h
AMD errata 400
"APIC Timer Interrupt Does Not Occur in Processor C-States"
is only mentioned in the revision guides for family 0fh and 10h
but we were checking for and disabling C1E on >= family 0fh.
Since family 16h all the bits of the Interrupt Pending MSR the
workaround uses are documented as read as zero. So this didn't cause
any problems on real hardware but did on EPYC based AWS t3a instances
according to Ilya Voronin who sent an initial patch to not attempt the
workaround on family 17h.
Tested on non-virtualised EPYC 7702P 17-31-00 by Hrvoje Popovski and
Ryzen 5 2600X 17-08-02 by myself.
ok mlarkin@
