CVSROOT: /cvs Module name: src Changes by: bl...@cvs.openbsd.org 2021/09/01 03:50:21
Modified files:
sys/arch/amd64/include: asm.h
Log message:
Older AMD CPUs that do not support IBRS need an lfence after ret
to stop speculation. This seems to be necessary when the branch
predictor hits the ret for the first time. In their white paper
to mitigate speculation attacks, AMD's retpoline example has an
explicit lfence. Adjust our retpoline assembly macro in the kernel.
OK guenther@ mortimer@ deraadt@
