CVSROOT: /cvs
Module name: src
Changes by: [email protected] 2022/01/18 04:36:21
Modified files:
sys/arch/armv7/marvell: mvpxa.c
sys/dev/acpi : sdhc_acpi.c
sys/dev/fdt : cdsdhc.c sdhc_fdt.c
sys/dev/pci : sdhc_pci.c
sys/dev/sdmmc : sdhc.c sdhcvar.h
Log message:
Improve how quirks are handled on sdhc(4)-compatible drivers. So far
we have passed a modified version of the contents in the capabilities
register if we wanted to override what sdhc(4) would otherwise read.
Unfortunately there's a second capabilities register that we did not
yet take into consideration, which is why to disable DDR50 support we
created a quirk flag in the softc. The sdhc(4) ACPI nodes have a way
to mask and set bits in both of the capabilities register, which is a
flexible approach to solving that issue and using that for our sdhc(4)
drivers even improves readability.
ok kettenis@
