CVSROOT: /cvs
Module name: src
Changes by: j...@cvs.openbsd.org 2022/06/28 06:11:41
Modified files:
sys/arch/amd64/include: cpu.h
sys/arch/amd64/amd64: cacheinfo.c
Removed files:
sys/arch/amd64/include: cacheinfo.h
Log message:
rewrite amd64 printing of cache details
Previously we looked at cpuid 0x80000005 for L1/TLB details
which Intel documents as reserved.
And cpuid 0x80000006 for L2 details.
Intel also encode cache details in cpuid 4.
AMD have mostly the same encoding with cpuid 0x8000001d
0x80000005/0x80000006 is used as a fallback.
Prompted by Intel Tiger Lake and Alder Lake machines
returning an associativity value of 7 from cpuid 0x80000006.
The previous code would print "disabled L2 cache", 7 is
documented by Intel as "See CPUID leaf 04H, sub-leaf 2".
tested by Hrvoje Popovski on EPYC 7413, and myself on various machines
ok mlarkin@
