CVSROOT: /cvs
Module name: src
Changes by: chel...@cvs.openbsd.org 2022/08/08 22:49:08
Modified files:
sys/arch/riscv64/include: cpu.h
sys/arch/riscv64/riscv64: clock.c
sys/arch/riscv64/dev: plic.c
Log message:
riscv64: trigger deferred timer interrupts from splx(9)
In order to move riscv64 to a machine-independent clock interrupt
subsystem, the riscv64 clock interrupt code needs to function without
any specific knowledge of the clock interrupt schedule.
The easiest way to achieve this (as we just did with powerpc and
powerpc64) is, if the timer interrupt fires while the CPU is at or
above IPL_CLOCK, defer clock interrupt work until the the timer
interrupt is logically unmasked in splx(9).
In particular, trigger the timer interrupt from plic_setipl() so the
interrupt, if any, is pending before we handle soft interrupts.
Because we're no longer deferring work until the next tick, we don't
need to count pending statclock ticks in struct cpu_info.
kettenis@ notes that the timer triggering code should be refactored
into more generic code when we add support for a non-plic(4) riscv64
machine.
Graciously fixed, compiled, and tested by jca@.
Link: https://marc.info/?l=openbsd-tech&m=165931635410276&w=2
ok kettenis@
