CVSROOT: /cvs
Module name: src
Changes by: kette...@cvs.openbsd.org 2023/09/19 13:15:08
Modified files:
sys/arch/riscv64/dev: stfclock.c
Log message:
Instead of adjusting PLL0 to scale the CPU frequency, use the divider
of the actual CPU clock. This prevents one of the GMAC0 clocks changing
when we change the CPU frequency, which would break one of the Ethernet
ports on the VisionFive 2 v1.2a.
However, since the firmware configures PLL0 to 1 GHz, we still need to
bump it up to 1.5 GHz in order to reach the highest supported CPU clock
rates.
ok jmatthew@, jca@, jsing@
