CVSROOT: /cvs
Module name: src
Changes by: [email protected] 2024/03/27 17:10:18
Modified files:
sys/arch/riscv64/include: bus.h
sys/arch/riscv64/riscv64: bus_space.c
Log message:
The RISC-V architecture specification says that memory read/writes are
not ordered with respect to mmio read/writes. This appears to happen on
T-Head C920 cores as I'm seeing interrupts being enabled before the lock
is released in mtx_leave() despite program order releasing the lock
before enabling interrupts. This is fixed by adding the necessary fences
in more or less the same places where Linux uses them.
ok patrick@, jca@
