CVSROOT: /cvs Module name: src Changes by: [email protected] 2025/08/04 06:34:41
Modified files:
sys/arch/amd64/amd64: trap.c
Log message:
Avoid implicit sign extension in vctrap()
port is uint16_t. Shifting promotes to signed 32bit integer. When
assigning to uint64_t sw_exitinfo1 the value gets sign extended.
Thus when "port << 16" is greater than 0x7fffffff the upper bits
of sw_exitinfo1 will be all 1. Therefore change port to uint64_t and
mask.
Coverity CID 1648416.
ok bluhm mlarkin
