CVSROOT: /cvs Module name: src Changes by: [email protected] 2025/10/09 14:08:49
Modified files:
sys/arch/riscv64/dev: stfclock.c
Log message:
Improve JH7110 support:
- Round to the nearest achievable clock rate instead of rounding down.
- Make sure we don't set a divider to zero.
- Fully initialize PLL0 when setting its rate.
- Bump PLL0 rate regardless of what the firmware configures it to.
This avoids issues with firmware based on upstream U-Boot.
ok jca@
