CVSROOT: /cvs Module name: src Changes by: [email protected] 2025/12/30 08:21:05
Modified files:
sys/arch/amd64/amd64: lapic.c
Log message:
On Intel CPUs writes to the x2APIC MSRs are non-serializing. This means
that writes done before sending an IPI may not be visible to other CPUs
because of out-of-order execution of the MSR write that triggers the IPI.
Add a "mfence; lfence" barrier like Linux has to prevent this unexpected
trap.
ok deraadt@, mlarkin@, mpi@
