CVSROOT: /cvs
Module name: src
Changes by: m...@cvs.openbsd.org 2010/11/24 14:16:28
Modified files:
sys/arch/mips64/include: _types.h cpu.h proc.h
sys/arch/mips64/mips64: cpu.c fp_emulate.c mips64_machdep.c
trap.c vm_machdep.c
Log message:
Floating-point emulation code for systems lacking proper FPU (i.e. Octeon),
enabled by option FPUEMUL.
This is pretty straightforward, except for conditional branch on FPU condition
codes emulation (bc1f/bc1fl/bc1t/bc1tl instructions): unlike most
RISC-with-delay-slots designs (m88k, sparc), the branch pipeline is not exposed
to the kernel on Mips, therefore we can not resume a branch without losing the
delay slot instruction.
Some other operating systems work around this issue by emulating the delay
slot instruction, but this is error-prone (and requires the kernel code to
be aware of all supported instructions of the processor it is currently running
on), some use dedicated breakpoints to single-step through the delay slot and
then resume the branch as expected, but this causes a lot of copy-on-write
allocations.
This code chooses a third path, of copying the delay slot instructions to run
toa special `magic' page, followed by a special trap instruction to give control
back to the kernel. This makes sure the instruction will actually be run by the
processor, and that no more than one page per process is wasted, regardless of
the number of branches to emulate.
Tested on octeon (big-endian) by syuu@ and on loongson (little-endian) by me.
Note that enabling option FPUEMUL in the kernel will completely disable the
hardware FPU, if there is one; there is currently no way to build a kernel
supporting both hardware and software FPU, and there is no reason to change
this until there is a strong need to support both.
