CVSROOT: /cvs
Module name: src
Changes by: [email protected] 2012/04/06 14:11:18
Modified files:
sys/arch/mips64/include: cache.h cpu.h pmap.h
sys/arch/mips64/mips64: cache_loongson2.S cache_r10k.S
cache_r4k.c cache_r5k.S cpu.c pmap.c
Log message:
Make the logic for PMAP_PREFER() and the logic, inside pmap, to do the
necessary cache coherency work wrt similar virtual indexes of different
physical pages, depending upon two distinct global variables, instead of
a shared one. R4000/R4400 VCE requires a 32KB mask for PMAP_PREFER, which
is otherwise not necessary for pmap coherency (especially since, on these
processors, only L1 uses virtual indexes, and the L1 size is not greater
than the page size, as we are using 16KB pages).
