CVSROOT: /cvs
Module name: src
Changes by: m...@cvs.openbsd.org 2014/03/31 14:21:19
Modified files:
sys/arch/loongson/include: cpu.h
sys/arch/mips64/include: cache.h cpu.h pmap.h
sys/arch/mips64/mips64: cache_loongson2.c cache_octeon.c
cache_r10k.c cache_r4k.c cache_r5k.c
cache_tfp.c pmap.c
sys/arch/octeon/include: cpu.h
Log message:
Due the virtually indexed nature of the L1 instruction cache on most mips
processors, every time a new text page is mapped in a pmap, the L1 I$ is
flushed for the va spanned by this page.
Since we map pages of our binaries upon demand, as they get faulted in, but
uvm_fault() tries to map the few neighbour pages, this can end up in a
bunch of pmap_enter() calls in a row, for executable mappings. If the L1
I$ is small enough, this can cause the whole L1 I$ cache to be flushed
several times.
Change pmap_enter() to postpone these flushes by only registering the
pending flushes, and have pmap_update() perform them. The cpu-specific
cache code can then optimize this to avoid unnecessary operations.
Tested on R4000SC, R4600SC, R5000SC, RM7000, R10000 with 4KB and 16KB
page sizes (coherent and non-coherent designs), and Loongson 2F by mikeb@ and
me. Should not affect anything on Octeon since there is no way to flush a
subset of I$ anyway.
