CVSROOT: /cvs Module name: src Changes by: [email protected] 2015/01/25 04:38:49
Modified files:
sys/dev : spdmem.c
Log message:
Correct a bit test for DDR2 CAS Latency and recognise CL7 and CL6.
While the spec only mentions bits for CL5->CL2 with the other
bits being marked 'TBD' it seems likely they are used now.
>From David Vasek.
