CVSROOT: /cvs
Module name: src
Changes by: patr...@cvs.openbsd.org 2017/02/22 15:55:27
Modified files:
sys/arch/arm64/arm64: bus_dma.c
sys/arch/arm64/dev: mainbus.c simplebus.c
sys/arch/arm64/include: bus.h
Log message:
The AMD Seattle SoC incorporates DMA coherent controllers, especially
AHCI, PCIe and Ethernet. Since these systems rely on cache snooping,
we must not map pages that are supposed to be coherent as uncacheable.
Instead if we have a cache coherent device, create a bus tag and mark
that tag as coherent. For users of that tag we can simply use normal,
cached memory.
ok kettenis@
