CVSROOT: /cvs
Module name: src
Changes by: kette...@cvs.openbsd.org 2017/04/02 12:06:57
Modified files:
sys/arch/arm64/arm64: pmap.c
Log message:
On ARMv8, the translation table walk is fully coherent so there is no
reason to explicitly flush the cache before invalidating the TLB. The
barrier that is included in out TLB flushing code should be enough to
guarantee that the TLB walking hardware sees the updated page table
contents, so the explicit barriers can go as well. Sanitize the code
immediately surrounding the removed bits while I'm there.
Tested by jsg@, ok drahn@, visa@
