CVSROOT: /cvs
Module name: src
Changes by: patr...@cvs.openbsd.org 2018/07/09 03:51:43
Modified files:
sys/arch/arm/cortex: ampintc.c amptimer.c files.cortex
Log message:
Implement ampintcmsi(4) in ampintc(4) to support MSI. The GICv2M is an
extension to the GIC controller, which is represented as subnode in the
device tree. There can be multiple GICv2Ms, so it makes sense to attach
those to ampintc(4) as some kind of simplebus. The GICv2M is simply an
interrupt generator that can be used by PCIe devices to ring the door
bell. There is no need for further configuration, we only need to find
out which SPIs we are allowed to use for MSI and to register an edge
triggered interrupt on a (randomly) allocated SPI.
Implement support for interrupt types. The GIC only seems to support
level triggered active-high or egdge triggered low-to-high interrupts.
We currently always configure them to be level triggered, which is a
sane default for most controllers. Since MSI interupts on the GIC are
edge triggered, we need to be able to parse the type information and to
configure the interrupt correspondingly.
ok kettenis@
