Jürgen, On Tue, Feb 19, 2008 at 10:49:42AM +0100, Andrea Paterniani wrote: > Subject: [patch-2.6.25-rc2-spi_imx] arm: SPI controller driver for Freescale > iMX > From: Andrea Paterniani <[EMAIL PROTECTED]> > > Kernel version: linux-2.6.25-rc2. > Patch description: > 1) Some comments changed and/or added. > 2) End of transfers is now managed on TXFIFO empty interrupt after the last > write to TXFIFO. This management shorten interrupt execution time removing > the waiting for TXFIFO emptying. > On TXFIFO empty interrupt the handler needs only to wait for the end of > ongoing transaction (polling SPI_CONTROL_XCH) to close transfer. > 2.1) Write only transfers are closed flushing RXFIFO. > 2.2) Read transfers are closed reading trailing bytes from RXFIFO. > 2.3) Read transfers where RXFIFO overrun occurred are closed flushing > RXFIFO and aborting message. > 3) Fifos are now flushed via SPI disable after the end of ongoing transaction.
How different is the i.MX1 SPI driver from our combined i.MX27/i.MX21 driver? Background: we have worked on i2c and SPI drivers for the i.MX27 this week, and it is almost finished. Robert -- Dipl.-Ing. Robert Schwebel | http://www.pengutronix.de Pengutronix - Linux Solutions for Science and Industry Handelsregister: Amtsgericht Hildesheim, HRA 2686 Hannoversche Str. 2, 31134 Hildesheim, Germany Phone: +49-5121-206917-0 | Fax: +49-5121-206917-9 ------------------------------------------------------------------------- This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/ _______________________________________________ spi-devel-general mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/spi-devel-general
