Hello Associates, We are having a new requirement for Engineers with DSP filter design/verification a with one of our major client here in Irvine ,CA. Please go through the details of the project and let me know if you have consultants available for this profile.
*Please forward resumes to **[email protected]*<[email protected]> *Job Title: Engineers with DSP filter design/verification Job Duration: 6+ Months City: Irvine State: CA Status: Need Candidates * *Description: * PHY Verification ¡V Datapath blocks verification Requirements - Extensive working experience with verification of PHY ASIC design with significant datapath DSP components - Working verification experience with the following area is a must - complex arithmetic design against bit-exact MATLAB and C/C++ system modeling - Must be familiar with - Verilog / System verilog verification environment - Common RTL/gate level simulations and coverage tools including VCS, Verdi - Experience in verification environment development for large ASIC multi-million gate SOC design, with close interaction with DSP system/firmware team. - Experience in developing ASIC test plans and hands on development of test benches. - Good understanding of IC design fundamentals. - Understanding of DSP concept/techniques including FFT, FIR/LMS - Ethernet interface protocol including XAUI/XFI/SGMII is highly desirable - Exposure to Ethernet Copper PHY design including 1GBaseT/10GBaseT is highly desirable. PHY Verification ¡V General/Top level testcase development Requirements - Hands-on experiment on top level verification for Baseband PHY ASIC with significant datapath DSP components, embedded controller and standard compliance interfaces is a must - Working verification experience with one of the following area is a must - designs requiring compliance to standard specifications and/or embedding processor core - Must be familiar with - System verilog verification environment -VMM or equivalent transactor based verification framework - Common RTL/gate level simulations and coverage tools including VCS, Verdi - Experience in developing ASIC test plans - Good understanding of IC design fundamentals. DSP filter design/verification, having used the C/Verilog model to verify the DSP filter datapath. Any relevant experience with Matlab is a plus. Thank you. Ram Kumar || SystemGuru, Inc || 900 Route 9 North, Suite 400, Woodbridge, NJ 07095 Direct: 610-621-1235 IM:[email protected] <im%[email protected]> | Web: www.SystemGuru.com <http://www.systemguru.com/> -- You received this message because you are subscribed to the Google Groups "SRAOSS REKS" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/sraoss-reks?hl=en.
