the bitrig master branch has been updated by patrick with 2 new commits: commit 91c77b7a4d6df8310f10fe2329ed3279104cca80 diff: https://github.com/bitrig/bitrig/commit/91c77b7 author: Patrick Wildt <[email protected]> date: Tue Jan 20 19:52:49 2015 +0100
arm: implement drain writebuf for L2. Uncached pages are still buffered in the L2 layer. To make sure data arrives in main memory, we need to also drain/sync it. "looks sane to me" drahn@ M sys/arch/arm/arm/bus_dma.c M sys/arch/arm/arm/cpufunc.c M sys/arch/arm/armv7/armv7_space.c M sys/arch/arm/cortex/arml2cc.c M sys/arch/arm/include/cpufunc.h commit 717387b315f8dda8fdfec46e9757f1e6a8bcaf34 diff: https://github.com/bitrig/bitrig/commit/717387b author: Patrick Wildt <[email protected]> date: Fri Feb 14 01:09:14 2014 +0100 arm: implement raw load and sync in bus dma Apparently RAW is not 100% coherent, so that we have to flush L1, L2 and writebuf. This is not very performant. We will need to find out how we can improve this. M sys/arch/arm/arm/bus_dma.c M sys/arch/arm/include/bus.h
