This patch doesn't apply to the .37 stable tree. If someone wants it applied there, please email the backport to [email protected]
thanks, greg k-h > commit: 58c5296991d233f2e492aa7a884635bba478cf12 > From: Luis R. Rodriguez <[email protected]> > Date: Thu, 13 Jan 2011 18:19:29 -0800 > Subject: [PATCH] ath9k_hw: ASPM interoperability fix for AR9380/AR9382 > > There is an interoperability with AR9382/AR9380 in L1 state with a > few root complexes which can cause a hang. This is fixed by > setting some work around bits on the PCIE PHY. We fix by using > a new ini array to modify these bits when the radio is idle. > > Cc: [email protected] > Cc: Jack Lee <[email protected]> > Cc: Carl Huang <[email protected]> > Cc: David Quan <[email protected]> > Cc: Nael Atallah <[email protected]> > Cc: Sarvesh Shrivastava <[email protected]> > Signed-off-by: Luis R. Rodriguez <[email protected]> > Signed-off-by: John W. Linville <[email protected]> > --- > .../net/wireless/ath/ath9k/ar9003_2p2_initvals.h | 2 +- > drivers/net/wireless/ath/ath9k/ar9003_hw.c | 4 ++-- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h > b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h > index 81f9cf2..9ecca93 100644 > --- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h > +++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h > @@ -1842,7 +1842,7 @@ static const u32 ar9300_2p2_soc_preamble[][2] = { > > static const u32 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2[][2] = { > /* Addr allmodes */ > - {0x00004040, 0x08212e5e}, > + {0x00004040, 0x0821265e}, > {0x00004040, 0x0008003b}, > {0x00004044, 0x00000000}, > }; > diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c > b/drivers/net/wireless/ath/ath9k/ar9003_hw.c > index 6137634..06fb2c8 100644 > --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c > +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c > @@ -146,8 +146,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) > /* Sleep Setting */ > > INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, > - ar9300PciePhy_clkreq_enable_L1_2p2, > - ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2), > + ar9300PciePhy_pll_on_clkreq_disable_L1_2p2, > + > ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2), > 2); > > /* Fast clock modal settings */ > > _______________________________________________ > stable mailing list > [email protected] > http://linux.kernel.org/mailman/listinfo/stable _______________________________________________ stable mailing list [email protected] http://linux.kernel.org/mailman/listinfo/stable
