This is a note to let you know that I've just added the patch titled
ARM: pxa168: correct nand pmu setting
to the 2.6.39-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm-pxa168-correct-nand-pmu-setting.patch
and it can be found in the queue-2.6.39 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.
>From 6662498e132dfa758925a160fd5ef80a083651c3 Mon Sep 17 00:00:00 2001
From: Lei Wen <[email protected]>
Date: Tue, 21 Jun 2011 05:37:47 -0700
Subject: ARM: pxa168: correct nand pmu setting
From: Lei Wen <[email protected]>
commit 6662498e132dfa758925a160fd5ef80a083651c3 upstream.
The original pair of <0x01db, 208000000> is invalid. Correct it to
the valid value.
The 6th bit of the NFC APMU register indicates NFC works whether
at 156Mhz or 78Mhz. So 0x19b indicates NFC works at 156Mhz, and
0x1db indicates it works at 78Mhz.
Signed-off-by: Lei Wen <[email protected]>
Signed-off-by: Eric Miao <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
arch/arm/mach-mmp/pxa168.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -79,7 +79,7 @@ static APBC_CLK(ssp4, PXA168_SSP4, 4, 0)
static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
-static APMU_CLK(nand, NAND, 0x01db, 208000000);
+static APMU_CLK(nand, NAND, 0x19b, 156000000);
static APMU_CLK(lcd, LCD, 0x7f, 312000000);
/* device and clock bindings */
Patches currently in stable-queue which might be from [email protected] are
queue-2.6.39/arm-pxa910-correct-nand-pmu-setting.patch
queue-2.6.39/arm-pxa168-correct-nand-pmu-setting.patch
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