This is a note to let you know that I've just added the patch titled
ARM: pxa910: correct nand pmu setting
to the 2.6.39-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm-pxa910-correct-nand-pmu-setting.patch
and it can be found in the queue-2.6.39 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <sta...@kernel.org> know about it.
>From d204b2c5b16df935fa9a546c528e168859fddcc0 Mon Sep 17 00:00:00 2001
From: Lei Wen <lei...@marvell.com>
Date: Tue, 21 Jun 2011 02:54:18 -0700
Subject: ARM: pxa910: correct nand pmu setting
From: Lei Wen <lei...@marvell.com>
commit d204b2c5b16df935fa9a546c528e168859fddcc0 upstream.
The original pair of <0x01db, 208000000> is invalid.
Correct to the valid value.
Signed-off-by: Lei Wen <lei...@marvell.com>
Signed-off-by: Eric Miao <eric.y.m...@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gre...@suse.de>
---
arch/arm/mach-mmp/pxa910.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -110,7 +110,7 @@ static APBC_CLK(pwm2, PXA910_PWM2, 1, 13
static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
-static APMU_CLK(nand, NAND, 0x01db, 208000000);
+static APMU_CLK(nand, NAND, 0x19b, 156000000);
static APMU_CLK(u2o, USB, 0x1b, 480000000);
/* device and clock bindings */
Patches currently in stable-queue which might be from lei...@marvell.com are
queue-2.6.39/arm-pxa910-correct-nand-pmu-setting.patch
queue-2.6.39/arm-pxa168-correct-nand-pmu-setting.patch
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