This is a note to let you know that I've just added the patch titled
drm/i915: gen7: Implement an L3 caching workaround.
to the 3.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-i915-gen7-implement-an-l3-caching-workaround.patch
and it can be found in the queue-3.0 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.
>From e4e0c058a19c41150d12ad2d3023b3cf09c5de67 Mon Sep 17 00:00:00 2001
From: Eugeni Dodonov <[email protected]>
Date: Wed, 8 Feb 2012 12:53:50 -0800
Subject: drm/i915: gen7: Implement an L3 caching workaround.
From: Eugeni Dodonov <[email protected]>
commit e4e0c058a19c41150d12ad2d3023b3cf09c5de67 upstream.
This adds two cache-related workarounds for Ivy Bridge which can lead to
3D ring hangs and corruptions.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41353
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44610
Tested-by: Eugeni Dodonov <[email protected]>
Signed-off-by: Eugeni Dodonov <[email protected]>
Signed-off-by: Kenneth Graunke <[email protected]>
Signed-off-by: Jesse Barnes <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
drivers/gpu/drm/i915/intel_display.c | 6 ++++++
2 files changed, 13 insertions(+)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2847,6 +2847,13 @@
#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
#define DISP_FBC_WM_DIS (1<<15)
+/* GEN7 chicken */
+#define GEN7_L3CNTLREG1 0xB01C
+#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C
+
+#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
+#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
+
/* PCH */
/* south display engine interrupt */
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7464,6 +7464,12 @@ static void ivybridge_init_clock_gating(
I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
+ /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
+ I915_WRITE(GEN7_L3CNTLREG1,
+ GEN7_WA_FOR_GEN7_L3_CONTROL);
+ I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
+ GEN7_WA_L3_CHICKEN_MODE);
+
for_each_pipe(pipe)
I915_WRITE(DSPCNTR(pipe),
I915_READ(DSPCNTR(pipe)) |
Patches currently in stable-queue which might be from [email protected]
are
queue-3.0/drm-i915-gen7-implement-rczunit-workaround.patch
queue-3.0/drm-i915-gen7-implement-an-l3-caching-workaround.patch
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