From: Nadav Haklai <nad...@marvell.com>
This patch has been added to the 3.18 stable tree. If you have any
objections, please let us know.
===============
This patch has been added to the 3.18 stable tree. If you have any
objections, please let us know.
===============
[ Upstream commit e96998fc200867f005dd14c7d1dd35e1107d4914 ]
According to the Armada 38x datasheet, the window base address
registers value is set in bits [31:4] of the register and corresponds
to the transaction address bits [47:20].
Therefore, the 32bit base address value should be shifted right by
20bits and left by 4bits, resulting in 16 bit shift right.
The bug as not been noticed yet because if the memory available on
the platform is less than 2GB, then the base address is zero.
[gregory.clem...@free-electrons.com: add extra-explanation]
Fixes: a3464ed2f14 (ata: ahci_mvebu: new driver for Marvell Armada 380
AHCI interfaces)
Signed-off-by: Nadav Haklai <nad...@marvell.com>
Reviewed-by: Omri Itach <om...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Tejun Heo <t...@kernel.org>
Signed-off-by: Sasha Levin <sasha.le...@oracle.com>
---
drivers/ata/ahci_mvebu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_mvebu.c
index 68672d2..e3267b7 100644
--- a/drivers/ata/ahci_mvebu.c
+++ b/drivers/ata/ahci_mvebu.c
@@ -43,7 +43,7 @@ static void ahci_mvebu_mbus_config(struct ahci_host_priv
*hpriv,
writel((cs->mbus_attr << 8) |
(dram->mbus_dram_target_id << 4) | 1,
hpriv->mmio + AHCI_WINDOW_CTRL(i));
- writel(cs->base, hpriv->mmio + AHCI_WINDOW_BASE(i));
+ writel(cs->base >> 16, hpriv->mmio + AHCI_WINDOW_BASE(i));
writel(((cs->size - 1) & 0xffff0000),
hpriv->mmio + AHCI_WINDOW_SIZE(i));
}
--
2.1.0
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