On Mon, 2015-02-11 at 01:30:31 UTC, Boqun Feng wrote: > According to memory-barriers.txt: > > > Any atomic operation that modifies some state in memory and returns > > information about the state (old or new) implies an SMP-conditional > > general memory barrier (smp_mb()) on each side of the actual > > operation ... > > Which mean these operations should be fully ordered. However on PPC, > PPC_ATOMIC_ENTRY_BARRIER is the barrier before the actual operation, > which is currently "lwsync" if SMP=y. The leading "lwsync" can not > guarantee fully ordered atomics, according to Paul Mckenney: > > https://lkml.org/lkml/2015/10/14/970 > > To fix this, we define PPC_ATOMIC_ENTRY_BARRIER as "sync" to guarantee > the fully-ordered semantics. > > This also makes futex atomics fully ordered, which can avoid possible > memory ordering problems if userspace code relies on futex system call > for fully ordered semantics. > > Cc: <[email protected]> # 3.4+ > Signed-off-by: Boqun Feng <[email protected]> > Reviewed-by: Paul E. McKenney <[email protected]> > Acked-by: Peter Zijlstra (Intel) <[email protected]>
Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/49e9cf3f0c04bf76ffa59242 cheers -- To unsubscribe from this list: send the line "unsubscribe stable" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
