This is a note to let you know that I've just added the patch titled

    parisc: optimize mtsp(0,sr) inline assembly

to the 3.10-stable tree which can be found at:
    
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     parisc-optimize-mtsp-0-sr-inline-assembly.patch
and it can be found in the queue-3.10 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.


>From 92b59929825d67db575043a76651865d16873b36 Mon Sep 17 00:00:00 2001
From: Helge Deller <[email protected]>
Date: Sat, 29 Jun 2013 22:08:03 +0200
Subject: parisc: optimize mtsp(0,sr) inline assembly

From: Helge Deller <[email protected]>

commit 92b59929825d67db575043a76651865d16873b36 upstream.

If the value which should be moved into a space register is zero, we can
optimize the inline assembly to become "mtsp %r0,%srX".

Signed-off-by: Helge Deller <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

---
 arch/parisc/include/asm/special_insns.h |    9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

--- a/arch/parisc/include/asm/special_insns.h
+++ b/arch/parisc/include/asm/special_insns.h
@@ -32,9 +32,12 @@ static inline void set_eiem(unsigned lon
        cr;                             \
 })
 
-#define mtsp(gr, cr) \
-       __asm__ __volatile__("mtsp %0,%1" \
+#define mtsp(val, cr) \
+       { if (__builtin_constant_p(val) && ((val) == 0)) \
+        __asm__ __volatile__("mtsp %%r0,%0" : : "i" (cr) : "memory"); \
+       else \
+        __asm__ __volatile__("mtsp %0,%1" \
                : /* no outputs */ \
-               : "r" (gr), "i" (cr) : "memory")
+               : "r" (val), "i" (cr) : "memory"); }
 
 #endif /* __PARISC_SPECIAL_INSNS_H */


Patches currently in stable-queue which might be from [email protected] are

queue-3.10/parisc-fix-lmmio-mismatch-between-pat-length-and-mask-register.patch
queue-3.10/parisc-document-the-shadow-registers.patch
queue-3.10/parisc-optimize-mtsp-0-sr-inline-assembly.patch
queue-3.10/parisc-ensure-volatile-space-register-sr1-is-not-clobbered.patch
queue-3.10/parisc-fix-gcc-miscompilation-in-pa_memcpy.patch
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