Author: neel
Date: Thu Apr 30 19:23:50 2015
New Revision: 282281
URL: https://svnweb.freebsd.org/changeset/base/282281
Log:
Advertise the MTRR feature via CPUID and emulate the minimal set of MTRR MSRs.
This is required for booting Windows guests.
Reported by: Leon Dang (ld...@nahannisys.com)
MFC after: 2 weeks
Modified:
head/sys/amd64/vmm/amd/svm_msr.c
head/sys/amd64/vmm/intel/vmx_msr.c
head/sys/amd64/vmm/x86.c
Modified: head/sys/amd64/vmm/amd/svm_msr.c
==============================================================================
--- head/sys/amd64/vmm/amd/svm_msr.c Thu Apr 30 18:23:38 2015
(r282280)
+++ head/sys/amd64/vmm/amd/svm_msr.c Thu Apr 30 19:23:50 2015
(r282281)
@@ -27,12 +27,18 @@
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
-#include <sys/types.h>
+#include <sys/param.h>
#include <sys/errno.h>
+#include <sys/systm.h>
+#include <sys/cpuset.h>
#include <machine/cpufunc.h>
#include <machine/specialreg.h>
+#include <machine/vmm.h>
+#include "svm.h"
+#include "vmcb.h"
+#include "svm_softc.h"
#include "svm_msr.h"
#ifndef MSR_AMDK8_IPM
@@ -105,6 +111,13 @@ svm_rdmsr(struct svm_softc *sc, int vcpu
int error = 0;
switch (num) {
+ case MSR_MTRRcap:
+ case MSR_MTRRdefType:
+ case MSR_MTRR4kBase ... MSR_MTRR4kBase + 8:
+ case MSR_MTRR16kBase ... MSR_MTRR16kBase + 1:
+ case MSR_MTRR64kBase:
+ *result = 0;
+ break;
case MSR_AMDK8_IPM:
*result = 0;
break;
@@ -122,6 +135,14 @@ svm_wrmsr(struct svm_softc *sc, int vcpu
int error = 0;
switch (num) {
+ case MSR_MTRRcap:
+ vm_inject_gp(sc->vm, vcpu);
+ break;
+ case MSR_MTRRdefType:
+ case MSR_MTRR4kBase ... MSR_MTRR4kBase + 8:
+ case MSR_MTRR16kBase ... MSR_MTRR16kBase + 1:
+ case MSR_MTRR64kBase:
+ break; /* Ignore writes */
case MSR_AMDK8_IPM:
/*
* Ignore writes to the "Interrupt Pending Message" MSR.
Modified: head/sys/amd64/vmm/intel/vmx_msr.c
==============================================================================
--- head/sys/amd64/vmm/intel/vmx_msr.c Thu Apr 30 18:23:38 2015
(r282280)
+++ head/sys/amd64/vmm/intel/vmx_msr.c Thu Apr 30 19:23:50 2015
(r282281)
@@ -396,6 +396,13 @@ vmx_rdmsr(struct vmx *vmx, int vcpuid, u
error = 0;
switch (num) {
+ case MSR_MTRRcap:
+ case MSR_MTRRdefType:
+ case MSR_MTRR4kBase ... MSR_MTRR4kBase + 8:
+ case MSR_MTRR16kBase ... MSR_MTRR16kBase + 1:
+ case MSR_MTRR64kBase:
+ *val = 0;
+ break;
case MSR_IA32_MISC_ENABLE:
*val = misc_enable;
break;
@@ -427,6 +434,14 @@ vmx_wrmsr(struct vmx *vmx, int vcpuid, u
error = 0;
switch (num) {
+ case MSR_MTRRcap:
+ vm_inject_gp(vmx->vm, vcpuid);
+ break;
+ case MSR_MTRRdefType:
+ case MSR_MTRR4kBase ... MSR_MTRR4kBase + 8:
+ case MSR_MTRR16kBase ... MSR_MTRR16kBase + 1:
+ case MSR_MTRR64kBase:
+ break; /* Ignore writes */
case MSR_IA32_MISC_ENABLE:
changed = val ^ misc_enable;
/*
Modified: head/sys/amd64/vmm/x86.c
==============================================================================
--- head/sys/amd64/vmm/x86.c Thu Apr 30 18:23:38 2015 (r282280)
+++ head/sys/amd64/vmm/x86.c Thu Apr 30 19:23:50 2015 (r282281)
@@ -289,9 +289,8 @@ x86_emulate_cpuid(struct vm *vm, int vcp
/*
* Machine check handling is done in the host.
- * Hide MTRR capability.
*/
- regs[3] &= ~(CPUID_MCA | CPUID_MCE | CPUID_MTRR);
+ regs[3] &= ~(CPUID_MCA | CPUID_MCE);
/*
* Hide the debug store capability.
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