Author: adrian
Date: Thu May 19 04:22:58 2016
New Revision: 300186
URL: https://svnweb.freebsd.org/changeset/base/300186
Log:
[bwn] rename TGS low registers to be consistent with naming scheme.
Modified:
head/sys/dev/bwn/if_bwn_phy_common.c
head/sys/dev/bwn/if_bwnreg.h
Modified: head/sys/dev/bwn/if_bwn_phy_common.c
==============================================================================
--- head/sys/dev/bwn/if_bwn_phy_common.c Thu May 19 04:11:49 2016
(r300185)
+++ head/sys/dev/bwn/if_bwn_phy_common.c Thu May 19 04:22:58 2016
(r300186)
@@ -186,9 +186,9 @@ bwn_mac_phy_clock_set(struct bwn_mac *ma
if (bwn_is_bus_siba(mac)) {
val = siba_read_4(sc->sc_dev, SIBA_TGSLOW);
if (enabled)
- val |= BWN_TMSLOW_MACPHYCLKEN;
+ val |= BWN_TGSLOW_MACPHYCLKEN;
else
- val &= ~BWN_TMSLOW_MACPHYCLKEN;
+ val &= ~BWN_TGSLOW_MACPHYCLKEN;
siba_write_4(sc->sc_dev, SIBA_TGSLOW, val);
}
}
Modified: head/sys/dev/bwn/if_bwnreg.h
==============================================================================
--- head/sys/dev/bwn/if_bwnreg.h Thu May 19 04:11:49 2016
(r300185)
+++ head/sys/dev/bwn/if_bwnreg.h Thu May 19 04:22:58 2016
(r300186)
@@ -97,8 +97,8 @@
/* SIBA control registers */
#define BWN_TGSLOW_PHYCLOCK_ENABLE 0x00040000
#define BWN_TGSLOW_PHYRESET 0x00080000
-#define BWN_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY
Clock Control Enable (rev >= 5) */
-#define BWN_TMSLOW_PLLREFSEL 0x00200000 /* PLL
Frequency Reference Select (rev >= 5) */
+#define BWN_TGSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY
Clock Control Enable (rev >= 5) */
+#define BWN_TGSLOW_PLLREFSEL 0x00200000 /* PLL
Frequency Reference Select (rev >= 5) */
/* PHY_BANDWIDTH: N-PHY only */
#define BWN_TGSLOW_PHY_BANDWIDTH 0x00C00000
#define BWN_TGSLOW_PHY_BANDWIDTH_10MHZ 0x00000000
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