Author: jhb
Date: Fri Dec 16 01:06:35 2016
New Revision: 310133
URL: https://svnweb.freebsd.org/changeset/base/310133
Log:
MFC 308690: Sync instruction cache's after writing user breakpoints on MIPS.
Add an implementation for pmaps_sync_icache() on MIPS that sync's the
instruction cache on all CPUs via smp_rendezvous() after a debugger
inserts a breakpoint via ptrace(PT_IO).
Modified:
stable/10/sys/mips/mips/pmap.c
Directory Properties:
stable/10/ (props changed)
Changes in other areas also in this revision:
Modified:
stable/11/sys/mips/mips/pmap.c
Directory Properties:
stable/11/ (props changed)
Modified: stable/10/sys/mips/mips/pmap.c
==============================================================================
--- stable/10/sys/mips/mips/pmap.c Fri Dec 16 00:35:59 2016
(r310132)
+++ stable/10/sys/mips/mips/pmap.c Fri Dec 16 01:06:35 2016
(r310133)
@@ -74,11 +74,7 @@ __FBSDID("$FreeBSD$");
#include <sys/proc.h>
#include <sys/rwlock.h>
#include <sys/sched.h>
-#ifdef SMP
#include <sys/smp.h>
-#else
-#include <sys/cpuset.h>
-#endif
#include <sys/sysctl.h>
#include <sys/vmmeter.h>
@@ -3203,9 +3199,19 @@ pmap_activate(struct thread *td)
critical_exit();
}
+static void
+pmap_sync_icache_one(void *arg __unused)
+{
+
+ mips_icache_sync_all();
+ mips_dcache_wbinv_all();
+}
+
void
pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
{
+
+ smp_rendezvous(NULL, pmap_sync_icache_one, NULL, NULL);
}
/*
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