Author: landonf Date: Fri Sep 15 19:56:21 2017 New Revision: 323621 URL: https://svnweb.freebsd.org/changeset/base/323621
Log: Add MIPS32/64 Rev2 CP0 intctl register definitions. Approved by: adrian (mentor) Differential Revision: https://reviews.freebsd.org/D12300 Modified: head/sys/mips/include/cpufunc.h head/sys/mips/include/cpuregs.h Modified: head/sys/mips/include/cpufunc.h ============================================================================== --- head/sys/mips/include/cpufunc.h Fri Sep 15 19:48:48 2017 (r323620) +++ head/sys/mips/include/cpufunc.h Fri Sep 15 19:56:21 2017 (r323621) @@ -279,6 +279,15 @@ MIPS_RW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1); MIPS_RW32_COP0(prid, MIPS_COP_0_PRID); /* XXX 64-bit? */ MIPS_RW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1); + +#if defined(CPU_MIPS24K) || defined(CPU_MIPS34K) || \ + defined(CPU_MIPS74K) || defined(CPU_MIPS1004K) || \ + defined(CPU_MIPS1074K) || defined(CPU_INTERAPTIV) || \ + defined(CPU_PROAPTIV) +/* MIPS32/64 r2 intctl */ +MIPS_RW32_COP0_SEL(intctl, MIPS_COP_0_INTCTL, 1); +#endif + #ifdef CPU_XBURST MIPS_RW32_COP0_SEL(xburst_mbox0, MIPS_COP_0_XBURST_MBOX, 0); MIPS_RW32_COP0_SEL(xburst_mbox1, MIPS_COP_0_XBURST_MBOX, 1); Modified: head/sys/mips/include/cpuregs.h ============================================================================== --- head/sys/mips/include/cpuregs.h Fri Sep 15 19:48:48 2017 (r323620) +++ head/sys/mips/include/cpuregs.h Fri Sep 15 19:56:21 2017 (r323621) @@ -468,6 +468,7 @@ * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high. * 11 MIPS_COP_0_COMPARE .333 Compare (against Count). * 12 MIPS_COP_0_STATUS 3333 Status register. + * 12/1 MIPS_COP_0_INTCTL ..33 Interrupt setup (MIPS32/64 r2). * 13 MIPS_COP_0_CAUSE 3333 Exception cause register. * 14 MIPS_COP_0_EXC_PC 3636 Exception PC. * 15 MIPS_COP_0_PRID 3333 Processor revision identifier. @@ -548,6 +549,7 @@ /* MIPS32/64 */ #define MIPS_COP_0_USERLOCAL _(4) /* sel 2 is userlevel register */ #define MIPS_COP_0_HWRENA _(7) +#define MIPS_COP_0_INTCTL _(12) #define MIPS_COP_0_DEBUG _(23) #define MIPS_COP_0_DEPC _(24) #define MIPS_COP_0_PERFCNT _(25) @@ -560,6 +562,16 @@ #define MIPS_MMU_TLB 0x01 /* Standard TLB */ #define MIPS_MMU_BAT 0x02 /* Standard BAT */ #define MIPS_MMU_FIXED 0x03 /* Standard fixed mapping */ + +/* + * IntCtl Register Fields + */ +#define MIPS_INTCTL_IPTI_MASK 0xE0000000 /* bits 31..29 timer intr # */ +#define MIPS_INTCTL_IPTI_SHIFT 29 +#define MIPS_INTCTL_IPPCI_MASK 0x1C000000 /* bits 26..29 perf counter intr # */ +#define MIPS_INTCTL_IPPCI_SHIFT 26 +#define MIPS_INTCTL_VS_MASK 0x000001F0 /* bits 5..9 vector spacing */ +#define MIPS_INTCTL_VS_SHIFT 4 /* * Config Register Fields _______________________________________________ svn-src-all@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscr...@freebsd.org"
