Author: manu
Date: Mon Oct 2 16:12:06 2017
New Revision: 324210
URL: https://svnweb.freebsd.org/changeset/base/324210
Log:
Allwinner A64 ccu: Use clock/reset IDs from dt-bindings
Do not redefines resets and clocks ID which are already in the
dt-bindings include directory. Those files are under dual licenced
under GPL2/MIT so use them directly.
Modified:
head/sys/arm/allwinner/clkng/ccu_a64.c
head/sys/arm/allwinner/clkng/ccu_a64.h
Modified: head/sys/arm/allwinner/clkng/ccu_a64.c
==============================================================================
--- head/sys/arm/allwinner/clkng/ccu_a64.c Mon Oct 2 15:56:45 2017
(r324209)
+++ head/sys/arm/allwinner/clkng/ccu_a64.c Mon Oct 2 16:12:06 2017
(r324210)
@@ -43,143 +43,178 @@ __FBSDID("$FreeBSD$");
#include <arm/allwinner/clkng/aw_clk_nkmp.h>
#include <arm/allwinner/clkng/aw_clk_prediv_mux.h>
+#include <gnu/dts/include/dt-bindings/clock/sun50i-a64-ccu.h>
+#include <gnu/dts/include/dt-bindings/reset/sun50i-a64-ccu.h>
+
#include "ccu_a64.h"
+/* Non-exported clocks */
+
+#define CLK_OSC_12M 0
+#define CLK_PLL_CPUX 1
+#define CLK_PLL_AUDIO_BASE 2
+#define CLK_PLL_AUDIO 3
+#define CLK_PLL_AUDIO_2X 4
+#define CLK_PLL_AUDIO_4X 5
+#define CLK_PLL_AUDIO_8X 6
+#define CLK_PLL_VIDEO0 7
+#define CLK_PLL_VIDEO0_2X 8
+#define CLK_PLL_VE 9
+#define CLK_PLL_DDR0 10
+#define CLK_PLL_PERIPH0_2X 12
+#define CLK_PLL_PERIPH1 13
+#define CLK_PLL_PERIPH1_2X 14
+#define CLK_PLL_VIDEO1 15
+#define CLK_PLL_GPU 16
+#define CLK_PLL_HSIC 18
+#define CLK_PLL_DE 19
+#define CLK_PLL_DDR1 20
+#define CLK_CPUX 21
+#define CLK_AXI 22
+#define CLK_APB 23
+#define CLK_AHB1 24
+#define CLK_APB1 25
+#define CLK_APB2 26
+#define CLK_AHB2 27
+#define CLK_DRAM 94
+
+#define CLK_MBUS 112
+
static struct aw_ccung_reset a64_ccu_resets[] = {
- CCU_RESET(A64_RST_USB_PHY0, 0x0cc, 0)
- CCU_RESET(A64_RST_USB_PHY1, 0x0cc, 1)
- CCU_RESET(A64_RST_USB_HSIC, 0x0cc, 2)
+ CCU_RESET(RST_USB_PHY0, 0x0cc, 0)
+ CCU_RESET(RST_USB_PHY1, 0x0cc, 1)
+ CCU_RESET(RST_USB_HSIC, 0x0cc, 2)
- CCU_RESET(A64_RST_BUS_MIPI_DSI, 0x2c0, 1)
- CCU_RESET(A64_RST_BUS_CE, 0x2c0, 5)
- CCU_RESET(A64_RST_BUS_DMA, 0x2c0, 6)
- CCU_RESET(A64_RST_BUS_MMC0, 0x2c0, 8)
- CCU_RESET(A64_RST_BUS_MMC1, 0x2c0, 9)
- CCU_RESET(A64_RST_BUS_MMC2, 0x2c0, 10)
- CCU_RESET(A64_RST_BUS_NAND, 0x2c0, 13)
- CCU_RESET(A64_RST_BUS_DRAM, 0x2c0, 14)
- CCU_RESET(A64_RST_BUS_EMAC, 0x2c0, 17)
- CCU_RESET(A64_RST_BUS_TS, 0x2c0, 18)
- CCU_RESET(A64_RST_BUS_HSTIMER, 0x2c0, 19)
- CCU_RESET(A64_RST_BUS_SPI0, 0x2c0, 20)
- CCU_RESET(A64_RST_BUS_SPI1, 0x2c0, 21)
- CCU_RESET(A64_RST_BUS_OTG, 0x2c0, 23)
- CCU_RESET(A64_RST_BUS_EHCI0, 0x2c0, 24)
- CCU_RESET(A64_RST_BUS_EHCI1, 0x2c0, 25)
- CCU_RESET(A64_RST_BUS_OHCI0, 0x2c0, 28)
- CCU_RESET(A64_RST_BUS_OHCI1, 0x2c0, 29)
+ CCU_RESET(RST_BUS_MIPI_DSI, 0x2c0, 1)
+ CCU_RESET(RST_BUS_CE, 0x2c0, 5)
+ CCU_RESET(RST_BUS_DMA, 0x2c0, 6)
+ CCU_RESET(RST_BUS_MMC0, 0x2c0, 8)
+ CCU_RESET(RST_BUS_MMC1, 0x2c0, 9)
+ CCU_RESET(RST_BUS_MMC2, 0x2c0, 10)
+ CCU_RESET(RST_BUS_NAND, 0x2c0, 13)
+ CCU_RESET(RST_BUS_DRAM, 0x2c0, 14)
+ CCU_RESET(RST_BUS_EMAC, 0x2c0, 17)
+ CCU_RESET(RST_BUS_TS, 0x2c0, 18)
+ CCU_RESET(RST_BUS_HSTIMER, 0x2c0, 19)
+ CCU_RESET(RST_BUS_SPI0, 0x2c0, 20)
+ CCU_RESET(RST_BUS_SPI1, 0x2c0, 21)
+ CCU_RESET(RST_BUS_OTG, 0x2c0, 23)
+ CCU_RESET(RST_BUS_EHCI0, 0x2c0, 24)
+ CCU_RESET(RST_BUS_EHCI1, 0x2c0, 25)
+ CCU_RESET(RST_BUS_OHCI0, 0x2c0, 28)
+ CCU_RESET(RST_BUS_OHCI1, 0x2c0, 29)
- CCU_RESET(A64_RST_BUS_VE, 0x2c4, 0)
- CCU_RESET(A64_RST_BUS_TCON0, 0x2c4, 3)
- CCU_RESET(A64_RST_BUS_TCON1, 0x2c4, 4)
- CCU_RESET(A64_RST_BUS_DEINTERLACE, 0x2c4, 5)
- CCU_RESET(A64_RST_BUS_CSI, 0x2c4, 8)
- CCU_RESET(A64_RST_BUS_HDMI0, 0x2c4, 10)
- CCU_RESET(A64_RST_BUS_HDMI1, 0x2c4, 11)
- CCU_RESET(A64_RST_BUS_DE, 0x2c4, 12)
- CCU_RESET(A64_RST_BUS_GPU, 0x2c4, 20)
- CCU_RESET(A64_RST_BUS_MSGBOX, 0x2c4, 21)
- CCU_RESET(A64_RST_BUS_SPINLOCK, 0x2c4, 22)
- CCU_RESET(A64_RST_BUS_DBG, 0x2c4, 31)
+ CCU_RESET(RST_BUS_VE, 0x2c4, 0)
+ CCU_RESET(RST_BUS_TCON0, 0x2c4, 3)
+ CCU_RESET(RST_BUS_TCON1, 0x2c4, 4)
+ CCU_RESET(RST_BUS_DEINTERLACE, 0x2c4, 5)
+ CCU_RESET(RST_BUS_CSI, 0x2c4, 8)
+ CCU_RESET(RST_BUS_HDMI0, 0x2c4, 10)
+ CCU_RESET(RST_BUS_HDMI1, 0x2c4, 11)
+ CCU_RESET(RST_BUS_DE, 0x2c4, 12)
+ CCU_RESET(RST_BUS_GPU, 0x2c4, 20)
+ CCU_RESET(RST_BUS_MSGBOX, 0x2c4, 21)
+ CCU_RESET(RST_BUS_SPINLOCK, 0x2c4, 22)
+ CCU_RESET(RST_BUS_DBG, 0x2c4, 31)
- CCU_RESET(A64_RST_BUS_LVDS, 0x2C8, 31)
+ CCU_RESET(RST_BUS_LVDS, 0x2C8, 31)
- CCU_RESET(A64_RST_BUS_CODEC, 0x2D0, 0)
- CCU_RESET(A64_RST_BUS_SPDIF, 0x2D0, 1)
- CCU_RESET(A64_RST_BUS_THS, 0x2D0, 8)
- CCU_RESET(A64_RST_BUS_I2S0, 0x2D0, 12)
- CCU_RESET(A64_RST_BUS_I2S1, 0x2D0, 13)
- CCU_RESET(A64_RST_BUS_I2S2, 0x2D0, 14)
+ CCU_RESET(RST_BUS_CODEC, 0x2D0, 0)
+ CCU_RESET(RST_BUS_SPDIF, 0x2D0, 1)
+ CCU_RESET(RST_BUS_THS, 0x2D0, 8)
+ CCU_RESET(RST_BUS_I2S0, 0x2D0, 12)
+ CCU_RESET(RST_BUS_I2S1, 0x2D0, 13)
+ CCU_RESET(RST_BUS_I2S2, 0x2D0, 14)
- CCU_RESET(A64_RST_BUS_I2C0, 0x2D8, 0)
- CCU_RESET(A64_RST_BUS_I2C1, 0x2D8, 1)
- CCU_RESET(A64_RST_BUS_I2C2, 0x2D8, 2)
- CCU_RESET(A64_RST_BUS_SCR, 0x2D8, 5)
- CCU_RESET(A64_RST_BUS_UART0, 0x2D8, 16)
- CCU_RESET(A64_RST_BUS_UART1, 0x2D8, 17)
- CCU_RESET(A64_RST_BUS_UART2, 0x2D8, 18)
- CCU_RESET(A64_RST_BUS_UART3, 0x2D8, 19)
- CCU_RESET(A64_RST_BUS_UART4, 0x2D8, 20)
+ CCU_RESET(RST_BUS_I2C0, 0x2D8, 0)
+ CCU_RESET(RST_BUS_I2C1, 0x2D8, 1)
+ CCU_RESET(RST_BUS_I2C2, 0x2D8, 2)
+ CCU_RESET(RST_BUS_SCR, 0x2D8, 5)
+ CCU_RESET(RST_BUS_UART0, 0x2D8, 16)
+ CCU_RESET(RST_BUS_UART1, 0x2D8, 17)
+ CCU_RESET(RST_BUS_UART2, 0x2D8, 18)
+ CCU_RESET(RST_BUS_UART3, 0x2D8, 19)
+ CCU_RESET(RST_BUS_UART4, 0x2D8, 20)
};
static struct aw_ccung_gate a64_ccu_gates[] = {
- CCU_GATE(A64_CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 0x60, 1)
- CCU_GATE(A64_CLK_BUS_CE, "bus-ce", "ahb1", 0x60, 5)
- CCU_GATE(A64_CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6)
- CCU_GATE(A64_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8)
- CCU_GATE(A64_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9)
- CCU_GATE(A64_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10)
- CCU_GATE(A64_CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13)
- CCU_GATE(A64_CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14)
- CCU_GATE(A64_CLK_BUS_EMAC, "bus-emac", "ahb2", 0x60, 16)
- CCU_GATE(A64_CLK_BUS_TS, "bus-ts", "ahb1", 0x60, 18)
- CCU_GATE(A64_CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19)
- CCU_GATE(A64_CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20)
- CCU_GATE(A64_CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21)
- CCU_GATE(A64_CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 23)
- CCU_GATE(A64_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 0x60, 24)
- CCU_GATE(A64_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 25)
- CCU_GATE(A64_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 0x60, 28)
- CCU_GATE(A64_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 0x60, 29)
+ CCU_GATE(CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 0x60, 1)
+ CCU_GATE(CLK_BUS_CE, "bus-ce", "ahb1", 0x60, 5)
+ CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6)
+ CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8)
+ CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9)
+ CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10)
+ CCU_GATE(CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13)
+ CCU_GATE(CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14)
+ CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb2", 0x60, 16)
+ CCU_GATE(CLK_BUS_TS, "bus-ts", "ahb1", 0x60, 18)
+ CCU_GATE(CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19)
+ CCU_GATE(CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20)
+ CCU_GATE(CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21)
+ CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 23)
+ CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 0x60, 24)
+ CCU_GATE(CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 25)
+ CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 0x60, 28)
+ CCU_GATE(CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 0x60, 29)
- CCU_GATE(A64_CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0)
- CCU_GATE(A64_CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 3)
- CCU_GATE(A64_CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 4)
- CCU_GATE(A64_CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 0x64, 5)
- CCU_GATE(A64_CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8)
- CCU_GATE(A64_CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11)
- CCU_GATE(A64_CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12)
- CCU_GATE(A64_CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20)
- CCU_GATE(A64_CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21)
- CCU_GATE(A64_CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22)
+ CCU_GATE(CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0)
+ CCU_GATE(CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 3)
+ CCU_GATE(CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 4)
+ CCU_GATE(CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 0x64, 5)
+ CCU_GATE(CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8)
+ CCU_GATE(CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11)
+ CCU_GATE(CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12)
+ CCU_GATE(CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20)
+ CCU_GATE(CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21)
+ CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22)
- CCU_GATE(A64_CLK_BUS_CODEC, "bus-codec", "apb1", 0x68, 0)
- CCU_GATE(A64_CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1)
- CCU_GATE(A64_CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5)
- CCU_GATE(A64_CLK_BUS_THS, "bus-ths", "apb1", 0x68, 8)
- CCU_GATE(A64_CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12)
- CCU_GATE(A64_CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13)
- CCU_GATE(A64_CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14)
+ CCU_GATE(CLK_BUS_CODEC, "bus-codec", "apb1", 0x68, 0)
+ CCU_GATE(CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1)
+ CCU_GATE(CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5)
+ CCU_GATE(CLK_BUS_THS, "bus-ths", "apb1", 0x68, 8)
+ CCU_GATE(CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12)
+ CCU_GATE(CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13)
+ CCU_GATE(CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14)
- CCU_GATE(A64_CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6C, 0)
- CCU_GATE(A64_CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6C, 1)
- CCU_GATE(A64_CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6C, 2)
- CCU_GATE(A64_CLK_BUS_SCR, "bus-src", "apb2", 0x6C, 5)
- CCU_GATE(A64_CLK_BUS_UART0, "bus-uart0", "apb2", 0x6C, 16)
- CCU_GATE(A64_CLK_BUS_UART1, "bus-uart1", "apb2", 0x6C, 17)
- CCU_GATE(A64_CLK_BUS_UART2, "bus-uart2", "apb2", 0x6C, 18)
- CCU_GATE(A64_CLK_BUS_UART3, "bus-uart3", "apb2", 0x6C, 19)
- CCU_GATE(A64_CLK_BUS_UART4, "bus-uart4", "apb2", 0x6C, 20)
+ CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6C, 0)
+ CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6C, 1)
+ CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6C, 2)
+ CCU_GATE(CLK_BUS_SCR, "bus-src", "apb2", 0x6C, 5)
+ CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x6C, 16)
+ CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x6C, 17)
+ CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x6C, 18)
+ CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x6C, 19)
+ CCU_GATE(CLK_BUS_UART4, "bus-uart4", "apb2", 0x6C, 20)
- CCU_GATE(A64_CLK_BUS_DBG, "bus-dbg", "ahb1", 0x70, 7)
+ CCU_GATE(CLK_BUS_DBG, "bus-dbg", "ahb1", 0x70, 7)
- CCU_GATE(A64_CLK_USB_PHY0, "usb-phy0", "osc24M", 0xcc, 8)
- CCU_GATE(A64_CLK_USB_PHY1, "usb-phy1", "osc24M", 0xcc, 9)
- CCU_GATE(A64_CLK_USB_HSIC, "usb-hsic", "pll_hsic", 0xcc, 10)
- CCU_GATE(A64_CLK_USB_HSIC_12M, "usb-hsic-12M", "osc12M", 0xcc, 11)
- CCU_GATE(A64_CLK_USB_OHCI0, "usb-ohci0", "osc12M", 0xcc, 16)
- CCU_GATE(A64_CLK_USB_OHCI1, "usb-ohci1", "usb-ohci0", 0xcc, 17)
+ CCU_GATE(CLK_USB_PHY0, "usb-phy0", "osc24M", 0xcc, 8)
+ CCU_GATE(CLK_USB_PHY1, "usb-phy1", "osc24M", 0xcc, 9)
+ CCU_GATE(CLK_USB_HSIC, "usb-hsic", "pll_hsic", 0xcc, 10)
+ CCU_GATE(CLK_USB_HSIC_12M, "usb-hsic-12M", "osc12M", 0xcc, 11)
+ CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "osc12M", 0xcc, 16)
+ CCU_GATE(CLK_USB_OHCI1, "usb-ohci1", "usb-ohci0", 0xcc, 17)
- CCU_GATE(A64_CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0)
- CCU_GATE(A64_CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1)
- CCU_GATE(A64_CLK_DRAM_DEINTERLACE, "dram-deinterlace", "dram", 0x100, 2)
- CCU_GATE(A64_CLK_DRAM_TS, "dram-ts", "dram", 0x100, 3)
+ CCU_GATE(CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0)
+ CCU_GATE(CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1)
+ CCU_GATE(CLK_DRAM_DEINTERLACE, "dram-deinterlace", "dram", 0x100, 2)
+ CCU_GATE(CLK_DRAM_TS, "dram-ts", "dram", 0x100, 3)
- CCU_GATE(A64_CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 31)
+ CCU_GATE(CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 31)
- CCU_GATE(A64_CLK_AC_DIG_4X, "ac-dig-4x", "pll_audio-4x", 0x140, 30)
- CCU_GATE(A64_CLK_AC_DIG, "ac-dig", "pll_audio", 0x140, 31)
+ CCU_GATE(CLK_AC_DIG_4X, "ac-dig-4x", "pll_audio-4x", 0x140, 30)
+ CCU_GATE(CLK_AC_DIG, "ac-dig", "pll_audio", 0x140, 31)
- CCU_GATE(A64_CLK_AVS, "avs", "osc24M", 0x144, 31)
+ CCU_GATE(CLK_AVS, "avs", "osc24M", 0x144, 31)
- CCU_GATE(A64_CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x154, 31)
+ CCU_GATE(CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x154, 31)
};
static const char *osc12m_parents[] = {"osc24M"};
FIXED_CLK(osc12m_clk,
- A64_CLK_OSC_12M, /* id */
- "osc12M", /* name */
- osc12m_parents, /* parent */
+ CLK_OSC_12M, /* id */
+ "osc12M", /* name */
+ osc12m_parents, /* parent */
0, /* freq */
1, /* mult */
2, /* div */
@@ -187,7 +222,7 @@ FIXED_CLK(osc12m_clk,
static const char *pll_cpux_parents[] = {"osc24M"};
NKMP_CLK(pll_cpux_clk,
- A64_CLK_PLL_CPUX, /* id */
+ CLK_PLL_CPUX, /* id */
"pll_cpux", pll_cpux_parents, /* name, parents */
0x00, /* offset */
8, 5, 0, 0, /* n factor */
@@ -200,7 +235,7 @@ NKMP_CLK(pll_cpux_clk,
static const char *pll_audio_parents[] = {"osc24M"};
NKMP_CLK(pll_audio_clk,
- A64_CLK_PLL_AUDIO, /* id */
+ CLK_PLL_AUDIO, /* id */
"pll_audio", pll_audio_parents, /* name, parents */
0x08, /* offset */
8, 7, 0, 0, /* n factor */
@@ -213,7 +248,7 @@ NKMP_CLK(pll_audio_clk,
static const char *pll_audio_mult_parents[] = {"pll_audio"};
FIXED_CLK(pll_audio_2x_clk,
- A64_CLK_PLL_AUDIO_2X, /* id */
+ CLK_PLL_AUDIO_2X, /* id */
"pll_audio-2x", /* name */
pll_audio_mult_parents, /* parent */
0, /* freq */
@@ -221,7 +256,7 @@ FIXED_CLK(pll_audio_2x_clk,
1, /* div */
0); /* flags */
FIXED_CLK(pll_audio_4x_clk,
- A64_CLK_PLL_AUDIO_4X, /* id */
+ CLK_PLL_AUDIO_4X, /* id */
"pll_audio-4x", /* name */
pll_audio_mult_parents, /* parent */
0, /* freq */
@@ -229,7 +264,7 @@ FIXED_CLK(pll_audio_4x_clk,
1, /* div */
0); /* flags */
FIXED_CLK(pll_audio_8x_clk,
- A64_CLK_PLL_AUDIO_8X, /* id */
+ CLK_PLL_AUDIO_8X, /* id */
"pll_audio-8x", /* name */
pll_audio_mult_parents, /* parent */
0, /* freq */
@@ -239,7 +274,7 @@ FIXED_CLK(pll_audio_8x_clk,
static const char *pll_video0_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_video0_clk,
- A64_CLK_PLL_VIDEO0, /* id */
+ CLK_PLL_VIDEO0, /* id */
"pll_video0", pll_video0_parents, /* name, parents */
0x10, /* offset */
8, 7, 0, 0, /* n factor */
@@ -251,7 +286,7 @@ NM_CLK_WITH_FRAC(pll_video0_clk,
static const char *pll_ve_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_ve_clk,
- A64_CLK_PLL_VE, /* id */
+ CLK_PLL_VE, /* id */
"pll_ve", pll_ve_parents, /* name, parents */
0x18, /* offset */
8, 7, 0, 0, /* n factor */
@@ -263,7 +298,7 @@ NM_CLK_WITH_FRAC(pll_ve_clk,
static const char *pll_ddr0_parents[] = {"osc24M"};
NKMP_CLK_WITH_UPDATE(pll_ddr0_clk,
- A64_CLK_PLL_DDR0, /* id */
+ CLK_PLL_DDR0, /* id */
"pll_ddr0", pll_ddr0_parents, /* name, parents */
0x20, /* offset */
8, 5, 0, 0, /* n factor */
@@ -278,7 +313,7 @@ NKMP_CLK_WITH_UPDATE(pll_ddr0_clk,
static const char *pll_periph0_2x_parents[] = {"osc24M"};
static const char *pll_periph0_parents[] = {"pll_periph0_2x"};
NKMP_CLK(pll_periph0_2x_clk,
- A64_CLK_PLL_PERIPH0_2X, /* id */
+ CLK_PLL_PERIPH0_2X, /* id */
"pll_periph0_2x", pll_periph0_2x_parents, /* name, parents */
0x28, /* offset */
8, 5, 0, 0, /* n factor */
@@ -289,7 +324,7 @@ NKMP_CLK(pll_periph0_2x_clk,
28, 1000, /* lock */
AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
FIXED_CLK(pll_periph0_clk,
- A64_CLK_PLL_PERIPH0, /* id */
+ CLK_PLL_PERIPH0, /* id */
"pll_periph0", /* name */
pll_periph0_parents, /* parent */
0, /* freq */
@@ -300,7 +335,7 @@ FIXED_CLK(pll_periph0_clk,
static const char *pll_periph1_2x_parents[] = {"osc24M"};
static const char *pll_periph1_parents[] = {"pll_periph1_2x"};
NKMP_CLK(pll_periph1_2x_clk,
- A64_CLK_PLL_PERIPH1_2X, /* id */
+ CLK_PLL_PERIPH1_2X, /* id */
"pll_periph1_2x", pll_periph1_2x_parents, /* name, parents */
0x2C, /* offset */
8, 5, 0, 0, /* n factor */
@@ -311,7 +346,7 @@ NKMP_CLK(pll_periph1_2x_clk,
28, 1000, /* lock */
AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
FIXED_CLK(pll_periph1_clk,
- A64_CLK_PLL_PERIPH1, /* id */
+ CLK_PLL_PERIPH1, /* id */
"pll_periph1", /* name */
pll_periph1_parents, /* parent */
0, /* freq */
@@ -321,7 +356,7 @@ FIXED_CLK(pll_periph1_clk,
static const char *pll_video1_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_video1_clk,
- A64_CLK_PLL_VIDEO1, /* id */
+ CLK_PLL_VIDEO1, /* id */
"pll_video1", pll_video1_parents, /* name, parents */
0x30, /* offset */
8, 7, 0, 0, /* n factor */
@@ -333,7 +368,7 @@ NM_CLK_WITH_FRAC(pll_video1_clk,
static const char *pll_gpu_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_gpu_clk,
- A64_CLK_PLL_GPU, /* id */
+ CLK_PLL_GPU, /* id */
"pll_gpu", pll_gpu_parents, /* name, parents */
0x38, /* offset */
8, 7, 0, 0, /* n factor */
@@ -347,7 +382,7 @@ NM_CLK_WITH_FRAC(pll_gpu_clk,
static const char *pll_hsic_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_hsic_clk,
- A64_CLK_PLL_HSIC, /* id */
+ CLK_PLL_HSIC, /* id */
"pll_hsic", pll_hsic_parents, /* name, parents */
0x44, /* offset */
8, 7, 0, 0, /* n factor */
@@ -359,7 +394,7 @@ NM_CLK_WITH_FRAC(pll_hsic_clk,
static const char *pll_de_parents[] = {"osc24M"};
NM_CLK_WITH_FRAC(pll_de_clk,
- A64_CLK_PLL_DE, /* id */
+ CLK_PLL_DE, /* id */
"pll_de", pll_de_parents, /* name, parents */
0x48, /* offset */
8, 7, 0, 0, /* n factor */
@@ -371,7 +406,7 @@ NM_CLK_WITH_FRAC(pll_de_clk,
static const char *pll_ddr1_parents[] = {"osc24M"};
NKMP_CLK_WITH_UPDATE(pll_ddr1_clk,
- A64_CLK_PLL_DDR1, /* id */
+ CLK_PLL_DDR1, /* id */
"pll_ddr1", pll_ddr1_parents, /* name, parents */
0x4C, /* offset */
8, 7, 0, 0, /* n factor */
@@ -385,13 +420,13 @@ NKMP_CLK_WITH_UPDATE(pll_ddr1_clk,
static const char *cpux_parents[] = {"osc32k", "osc24M", "pll_cpux"};
MUX_CLK(cpux_clk,
- A64_CLK_CPUX, /* id */
+ CLK_CPUX, /* id */
"cpux", cpux_parents, /* name, parents */
0x50, 16, 2); /* offset, shift, width */
static const char *axi_parents[] = {"cpux"};
DIV_CLK(axi_clk,
- A64_CLK_AXI, /* id */
+ CLK_AXI, /* id */
"axi", axi_parents, /* name, parents */
0x50, /* offset */
0, 2, /* shift, width */
@@ -399,14 +434,14 @@ DIV_CLK(axi_clk,
static const char *apb_parents[] = {"cpux"};
DIV_CLK(apb_clk,
- A64_CLK_APB, /* id */
+ CLK_APB, /* id */
"apb", apb_parents, /* name, parents */
0x50, /* offset */
8, 2, /* shift, width */
0, NULL); /* flags, div table */
static const char *ahb1_parents[] = {"osc32k", "osc24M", "axi", "pll_periph0"};
-PREDIV_CLK(ahb1_clk, A64_CLK_AHB1, /* id */
+PREDIV_CLK(ahb1_clk, CLK_AHB1, /* id */
"ahb1", ahb1_parents, /* name,
parents */
0x54, /* offset */
12, 2, /* mux */
@@ -423,7 +458,7 @@ static struct clk_div_table apb1_div_table[] = {
{ },
};
DIV_CLK(apb1_clk,
- A64_CLK_APB1, /* id */
+ CLK_APB1, /* id */
"apb1", apb1_parents, /* name, parents */
0x54, /* offset */
8, 2, /* shift, width */
@@ -432,7 +467,7 @@ DIV_CLK(apb1_clk,
static const char *apb2_parents[] = {"osc32k", "osc24M", "pll_periph0_2x",
"pll_periph0_2x"};
NM_CLK(apb2_clk,
- A64_CLK_APB2, /* id */
+ CLK_APB2, /* id */
"apb2", apb2_parents, /* name, parents */
0x58, /* offset */
16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
@@ -442,7 +477,7 @@ NM_CLK(apb2_clk,
AW_CLK_HAS_MUX);
static const char *ahb2_parents[] = {"ahb1", "pll_periph0"};
-PREDIV_CLK(ahb2_clk, A64_CLK_AHB2, /* id */
+PREDIV_CLK(ahb2_clk, CLK_AHB2, /* id */
"ahb2", ahb2_parents, /* name,
parents */
0x5c, /* offset */
0, 2, /* mux */
@@ -452,7 +487,7 @@ PREDIV_CLK(ahb2_clk, A64_CLK_AHB2,
/* id */
static const char *mod_parents[] = {"osc24M", "pll_periph0_2x",
"pll_periph1_2x"};
NM_CLK(nand_clk,
- A64_CLK_NAND, "nand", mod_parents, /* id, name, parents */
+ CLK_NAND, "nand", mod_parents, /* id, name, parents */
0x80, /* offset */
16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
0, 4, 0, 0, /* m factor */
@@ -461,7 +496,7 @@ NM_CLK(nand_clk,
AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */
NM_CLK(mmc0_clk,
- A64_CLK_MMC0, "mmc0", mod_parents, /* id, name, parents */
+ CLK_MMC0, "mmc0", mod_parents, /* id, name, parents */
0x88, /* offset */
16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
0, 4, 0, 0, /* m factor */
@@ -471,7 +506,7 @@ NM_CLK(mmc0_clk,
AW_CLK_REPARENT); /* flags */
NM_CLK(mmc1_clk,
- A64_CLK_MMC1, "mmc1", mod_parents, /* id, name, parents */
+ CLK_MMC1, "mmc1", mod_parents, /* id, name, parents */
0x8c, /* offset */
16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
0, 4, 0, 0, /* m factor */
@@ -481,7 +516,7 @@ NM_CLK(mmc1_clk,
AW_CLK_REPARENT); /* flags */
NM_CLK(mmc2_clk,
- A64_CLK_MMC2, "mmc2", mod_parents, /* id, name, parents */
+ CLK_MMC2, "mmc2", mod_parents, /* id, name, parents */
0x90, /* offset */
16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
0, 4, 0, 0, /* m factor */
@@ -492,7 +527,7 @@ NM_CLK(mmc2_clk,
static const char *ts_parents[] = {"osc24M", "pll_periph0"};
NM_CLK(ts_clk,
- A64_CLK_TS, "ts", ts_parents, /* id, name, parents */
+ CLK_TS, "ts", ts_parents, /* id, name, parents */
0x98, /* offset */
16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
0, 4, 0, 0, /* m factor */
@@ -501,7 +536,7 @@ NM_CLK(ts_clk,
AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */
NM_CLK(ce_clk,
- A64_CLK_CE, "ce", mod_parents, /* id, name, parents */
+ CLK_CE, "ce", mod_parents, /* id, name, parents */
0x9C, /* offset */
16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
0, 4, 0, 0, /* m factor */
@@ -510,7 +545,7 @@ NM_CLK(ce_clk,
AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */
NM_CLK(spi0_clk,
- A64_CLK_SPI0, "spi0", mod_parents, /* id, name, parents */
+ CLK_SPI0, "spi0", mod_parents, /* id, name, parents */
0xA0, /* offset */
16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
0, 4, 0, 0, /* m factor */
@@ -520,7 +555,7 @@ NM_CLK(spi0_clk,
AW_CLK_REPARENT); /* flags */
NM_CLK(spi1_clk,
- A64_CLK_SPI1, "spi1", mod_parents, /* id, name, parents */
+ CLK_SPI1, "spi1", mod_parents, /* id, name, parents */
0xA4, /* offset */
16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
0, 4, 0, 0, /* m factor */
@@ -542,7 +577,7 @@ MUX_CLK(i2s2mux_clk,
static const char *spdif_parents[] = {"pll_audio"};
NM_CLK(spdif_clk,
- A64_CLK_SPDIF, "spdif", spdif_parents, /* id, name, parents */
+ CLK_SPDIF, "spdif", spdif_parents, /* id, name, parents */
0xC0, /* offset */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake); */
0, 4, 0, 0, /* m factor */
@@ -555,7 +590,7 @@ NM_CLK(spdif_clk,
/* DRAM needs update bit */
static const char *dram_parents[] = {"pll_ddr0", "pll_ddr1"};
NM_CLK(dram_clk,
- A64_CLK_DRAM, "dram", dram_parents, /* id, name, parents */
+ CLK_DRAM, "dram", dram_parents, /* id, name, parents */
0xF4, /* offset */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
0, 2, 0, 0, /* m factor */
@@ -565,7 +600,7 @@ NM_CLK(dram_clk,
static const char *de_parents[] = {"pll_periph0_2x", "pll_de"};
NM_CLK(de_clk,
- A64_CLK_DE, "de", de_parents, /* id, name, parents */
+ CLK_DE, "de", de_parents, /* id, name, parents */
0x104, /* offset */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
0, 4, 0, 0, /* m factor */
@@ -577,7 +612,7 @@ NM_CLK(de_clk,
static const char *deinterlace_parents[] = {"pll_periph0", "pll_periph1"};
NM_CLK(deinterlace_clk,
- A64_CLK_DEINTERLACE, "deinterlace", deinterlace_parents, /* id, name,
parents */
+ CLK_DEINTERLACE, "deinterlace", deinterlace_parents, /* id, name,
parents */
0x124, /* offset */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
0, 4, 0, 0, /* m factor */
@@ -587,7 +622,7 @@ NM_CLK(deinterlace_clk,
static const char *csi_sclk_parents[] = {"pll_periph0", "pll_periph1"};
NM_CLK(csi_sclk_clk,
- A64_CLK_CSI_SCLK, "csi-sclk", csi_sclk_parents, /* id, name, parents */
+ CLK_CSI_SCLK, "csi-sclk", csi_sclk_parents, /* id, name, parents */
0x134, /* offset */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
16, 4, 0, 0, /* m factor */
@@ -597,7 +632,7 @@ NM_CLK(csi_sclk_clk,
static const char *csi_mclk_parents[] = {"osc24M", "pll_video0",
"pll_periph1"};
NM_CLK(csi_mclk_clk,
- A64_CLK_CSI_MCLK, "csi-mclk", csi_mclk_parents, /* id, name, parents */
+ CLK_CSI_MCLK, "csi-mclk", csi_mclk_parents, /* id, name, parents */
0x134, /* offset */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
0, 4, 0, 0, /* m factor */
@@ -607,7 +642,7 @@ NM_CLK(csi_mclk_clk,
static const char *ve_parents[] = {"pll_ve"};
NM_CLK(ve_clk,
- A64_CLK_VE, "ve", ve_parents, /* id, name, parents */
+ CLK_VE, "ve", ve_parents, /* id, name, parents */
0x13C, /* offset */
16, 3, 0, 0, /* n factor */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
@@ -617,7 +652,7 @@ NM_CLK(ve_clk,
static const char *hdmi_parents[] = {"pll_video0"};
NM_CLK(hdmi_clk,
- A64_CLK_HDMI, "hdmi", hdmi_parents, /* id, name, parents */
+ CLK_HDMI, "hdmi", hdmi_parents, /* id, name, parents */
0x150, /* offset */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
0, 4, 0, 0, /* m factor */
@@ -627,7 +662,7 @@ NM_CLK(hdmi_clk,
static const char *mbus_parents[] = {"osc24M", "pll_periph0_2x", "pll_ddr0"};
NM_CLK(mbus_clk,
- A64_CLK_MBUS, "mbus", mbus_parents, /* id, name, parents */
+ CLK_MBUS, "mbus", mbus_parents, /* id, name, parents */
0x15C, /* offset */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
0, 3, 0, 0, /* m factor */
@@ -637,7 +672,7 @@ NM_CLK(mbus_clk,
static const char *gpu_parents[] = {"pll_gpu"};
NM_CLK(gpu_clk,
- A64_CLK_GPU, "gpu", gpu_parents, /* id, name, parents */
+ CLK_GPU, "gpu", gpu_parents, /* id, name, parents */
0x1A0, /* offset */
0, 2, 0, 0, /* n factor */
0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
Modified: head/sys/arm/allwinner/clkng/ccu_a64.h
==============================================================================
--- head/sys/arm/allwinner/clkng/ccu_a64.h Mon Oct 2 15:56:45 2017
(r324209)
+++ head/sys/arm/allwinner/clkng/ccu_a64.h Mon Oct 2 16:12:06 2017
(r324210)
@@ -29,176 +29,6 @@
#ifndef __CCU_A64_H__
#define __CCU_A64_H__
-#define A64_RST_USB_PHY0 0
-#define A64_RST_USB_PHY1 1
-#define A64_RST_USB_HSIC 2
-#define A64_RST_DRAM 3
-#define A64_RST_MBUS 4
-#define A64_RST_BUS_MIPI_DSI 5
-#define A64_RST_BUS_CE 6
-#define A64_RST_BUS_DMA 7
-#define A64_RST_BUS_MMC0 8
-#define A64_RST_BUS_MMC1 9
-#define A64_RST_BUS_MMC2 10
-#define A64_RST_BUS_NAND 11
-#define A64_RST_BUS_DRAM 12
-#define A64_RST_BUS_EMAC 13
-#define A64_RST_BUS_TS 14
-#define A64_RST_BUS_HSTIMER 15
-#define A64_RST_BUS_SPI0 16
-#define A64_RST_BUS_SPI1 17
-#define A64_RST_BUS_OTG 18
-#define A64_RST_BUS_EHCI0 19
-#define A64_RST_BUS_EHCI1 20
-#define A64_RST_BUS_OHCI0 21
-#define A64_RST_BUS_OHCI1 22
-#define A64_RST_BUS_VE 23
-#define A64_RST_BUS_TCON0 24
-#define A64_RST_BUS_TCON1 25
-#define A64_RST_BUS_DEINTERLACE 26
-#define A64_RST_BUS_CSI 27
-#define A64_RST_BUS_HDMI0 28
-#define A64_RST_BUS_HDMI1 29
-#define A64_RST_BUS_DE 30
-#define A64_RST_BUS_GPU 31
-#define A64_RST_BUS_MSGBOX 32
-#define A64_RST_BUS_SPINLOCK 33
-#define A64_RST_BUS_DBG 34
-#define A64_RST_BUS_LVDS 35
-#define A64_RST_BUS_CODEC 36
-#define A64_RST_BUS_SPDIF 37
-#define A64_RST_BUS_THS 38
-#define A64_RST_BUS_I2S0 39
-#define A64_RST_BUS_I2S1 40
-#define A64_RST_BUS_I2S2 41
-#define A64_RST_BUS_I2C0 42
-#define A64_RST_BUS_I2C1 43
-#define A64_RST_BUS_I2C2 44
-#define A64_RST_BUS_SCR 45
-#define A64_RST_BUS_UART0 46
-#define A64_RST_BUS_UART1 47
-#define A64_RST_BUS_UART2 48
-#define A64_RST_BUS_UART3 49
-#define A64_RST_BUS_UART4 50
-
-#define A64_CLK_OSC_12M 0
-#define A64_CLK_PLL_CPUX 1
-#define A64_CLK_PLL_AUDIO_BASE 2
-#define A64_CLK_PLL_AUDIO 3
-#define A64_CLK_PLL_AUDIO_2X 4
-#define A64_CLK_PLL_AUDIO_4X 5
-#define A64_CLK_PLL_AUDIO_8X 6
-#define A64_CLK_PLL_VIDEO0 7
-#define A64_CLK_PLL_VIDEO0_2X 8
-#define A64_CLK_PLL_VE 9
-#define A64_CLK_PLL_DDR0 10
-#define A64_CLK_PLL_PERIPH0 11
-#define A64_CLK_PLL_PERIPH0_2X 12
-#define A64_CLK_PLL_PERIPH1 13
-#define A64_CLK_PLL_PERIPH1_2X 14
-#define A64_CLK_PLL_VIDEO1 15
-#define A64_CLK_PLL_GPU 16
-#define A64_CLK_PLL_MIPI 17
-#define A64_CLK_PLL_HSIC 18
-#define A64_CLK_PLL_DE 19
-#define A64_CLK_PLL_DDR1 20
-#define A64_CLK_CPUX 21
-#define A64_CLK_AXI 22
-#define A64_CLK_APB 23
-#define A64_CLK_AHB1 24
-#define A64_CLK_APB1 25
-#define A64_CLK_APB2 26
-#define A64_CLK_AHB2 27
-#define A64_CLK_BUS_MIPI_DSI 28
-#define A64_CLK_BUS_CE 29
-#define A64_CLK_BUS_DMA 30
-#define A64_CLK_BUS_MMC0 31
-#define A64_CLK_BUS_MMC1 32
-#define A64_CLK_BUS_MMC2 33
-#define A64_CLK_BUS_NAND 34
-#define A64_CLK_BUS_DRAM 35
-#define A64_CLK_BUS_EMAC 36
-#define A64_CLK_BUS_TS 37
-#define A64_CLK_BUS_HSTIMER 38
-#define A64_CLK_BUS_SPI0 39
-#define A64_CLK_BUS_SPI1 40
-#define A64_CLK_BUS_OTG 41
-#define A64_CLK_BUS_EHCI0 42
-#define A64_CLK_BUS_EHCI1 43
-#define A64_CLK_BUS_OHCI0 44
-#define A64_CLK_BUS_OHCI1 45
-#define A64_CLK_BUS_VE 46
-#define A64_CLK_BUS_TCON0 47
-#define A64_CLK_BUS_TCON1 48
-#define A64_CLK_BUS_DEINTERLACE 49
-#define A64_CLK_BUS_CSI 50
-#define A64_CLK_BUS_HDMI 51
-#define A64_CLK_BUS_DE 52
-#define A64_CLK_BUS_GPU 53
-#define A64_CLK_BUS_MSGBOX 54
-#define A64_CLK_BUS_SPINLOCK 55
-#define A64_CLK_BUS_CODEC 56
-#define A64_CLK_BUS_SPDIF 57
-#define A64_CLK_BUS_PIO 58
-#define A64_CLK_BUS_THS 59
-#define A64_CLK_BUS_I2S0 60
-#define A64_CLK_BUS_I2S1 61
-#define A64_CLK_BUS_I2S2 62
-#define A64_CLK_BUS_I2C0 63
-#define A64_CLK_BUS_I2C1 64
-#define A64_CLK_BUS_I2C2 65
-#define A64_CLK_BUS_SCR 66
-#define A64_CLK_BUS_UART0 67
-#define A64_CLK_BUS_UART1 68
-#define A64_CLK_BUS_UART2 69
-#define A64_CLK_BUS_UART3 70
-#define A64_CLK_BUS_UART4 71
-#define A64_CLK_BUS_DBG 72
-#define A64_CLK_THS 73
-#define A64_CLK_NAND 74
-#define A64_CLK_MMC0 75
-#define A64_CLK_MMC1 76
-#define A64_CLK_MMC2 77
-#define A64_CLK_TS 78
-#define A64_CLK_CE 79
-#define A64_CLK_SPI0 80
-#define A64_CLK_SPI1 81
-#define A64_CLK_I2S0 82
-#define A64_CLK_I2S1 83
-#define A64_CLK_I2S2 84
-#define A64_CLK_SPDIF 85
-#define A64_CLK_USB_PHY0 86
-#define A64_CLK_USB_PHY1 87
-#define A64_CLK_USB_HSIC 88
-#define A64_CLK_USB_HSIC_12M 89
-#define A64_CLK_USB_OHCI0_12M 90
-#define A64_CLK_USB_OHCI0 91
-#define A64_CLK_USB_OHCI1_12M 92
-#define A64_CLK_USB_OHCI1 93
-#define A64_CLK_DRAM 94
-#define A64_CLK_DRAM_VE 95
-#define A64_CLK_DRAM_CSI 96
-#define A64_CLK_DRAM_DEINTERLACE 97
-#define A64_CLK_DRAM_TS 98
-#define A64_CLK_DE 99
-#define A64_CLK_TCON0 100
-#define A64_CLK_TCON1 101
-#define A64_CLK_DEINTERLACE 102
-#define A64_CLK_CSI_MISC 103
-#define A64_CLK_CSI_SCLK 104
-#define A64_CLK_CSI_MCLK 105
-#define A64_CLK_VE 106
-#define A64_CLK_AC_DIG 107
-#define A64_CLK_AC_DIG_4X 108
-#define A64_CLK_AVS 109
-#define A64_CLK_HDMI 110
-#define A64_CLK_HDMI_DDC 111
-
-#define A64_CLK_MBUS 112
-
-#define A64_CLK_DSI_DPHY 113
-#define A64_CLK_GPU 114
-
void ccu_a64_register_clocks(struct aw_ccung_softc *sc);
#endif /* __CCU_A64_H__ */
_______________________________________________
svn-src-all@freebsd.org mailing list
https://lists.freebsd.org/mailman/listinfo/svn-src-all
To unsubscribe, send any mail to "svn-src-all-unsubscr...@freebsd.org"
