Author: mw Date: Wed Apr 4 12:54:18 2018 New Revision: 332017 URL: https://svnweb.freebsd.org/changeset/base/332017
Log: Change reg in Marvell Armada38X pcie FDT Ranges in pcie-controller are unused, so could be changed to match Linux device tree represntation. Same with interrupt-cells and interrupt-parent. In PCI controller driver ocd_data are used for matching driver and choose proper resources acquisition function. fdt_win_process_child have new argument which provide information about fdt node containing addresses of MMIO registers. Submitted by: Rafal Kozik <r...@semihalf.com> Reviewed by: manu [DT part] Obtained from: Semihalf Sponsored by: Stormshield Differential Revision: https://reviews.freebsd.org/D14751 Modified: head/sys/arm/mv/mv_common.c head/sys/arm/mv/mv_pci_ctrl.c head/sys/dts/arm/armada-380.dtsi head/sys/dts/arm/armada-385.dtsi Modified: head/sys/arm/mv/mv_common.c ============================================================================== --- head/sys/arm/mv/mv_common.c Wed Apr 4 12:47:41 2018 (r332016) +++ head/sys/arm/mv/mv_common.c Wed Apr 4 12:54:18 2018 (r332017) @@ -176,7 +176,7 @@ int gic_decode_fdt(phandle_t iparent, pcell_t *intr, i static int win_cpu_from_dt(void); static int fdt_win_setup(void); -static int fdt_win_process_child(phandle_t, struct soc_node_spec *); +static int fdt_win_process_child(phandle_t, struct soc_node_spec *, const char*); static uint32_t dev_mask = 0; static int cpu_wins_no = 0; @@ -2757,7 +2757,7 @@ fdt_win_process(phandle_t child) if (!ofw_bus_node_is_compatible(child, soc_nodes[i].compat)) continue; - ret = fdt_win_process_child(child, &soc_nodes[i]); + ret = fdt_win_process_child(child, &soc_nodes[i], "reg"); if (ret != 0) return (ret); } @@ -2766,7 +2766,8 @@ fdt_win_process(phandle_t child) } static int -fdt_win_process_child(phandle_t child, struct soc_node_spec *soc_node) +fdt_win_process_child(phandle_t child, struct soc_node_spec *soc_node, + const char* mimo_reg_source) { int addr_cells, size_cells; pcell_t reg[8]; @@ -2778,8 +2779,7 @@ fdt_win_process_child(phandle_t child, struct soc_node if ((sizeof(pcell_t) * (addr_cells + size_cells)) > sizeof(reg)) return (ENOMEM); - - if (OF_getprop(child, "reg", ®, sizeof(reg)) <= 0) + if (OF_getprop(child, mimo_reg_source, ®, sizeof(reg)) <= 0) return (EINVAL); if (addr_cells <= 2) @@ -2836,7 +2836,8 @@ fdt_win_setup(void) child_pci = OF_child(child); while (child_pci != 0) { err = fdt_win_process_child(child_pci, - &soc_nodes[SOC_NODE_PCIE_ENTRY_IDX]); + &soc_nodes[SOC_NODE_PCIE_ENTRY_IDX], + "assigned-addresses"); if (err != 0) return (err); Modified: head/sys/arm/mv/mv_pci_ctrl.c ============================================================================== --- head/sys/arm/mv/mv_pci_ctrl.c Wed Apr 4 12:47:41 2018 (r332016) +++ head/sys/arm/mv/mv_pci_ctrl.c Wed Apr 4 12:54:18 2018 (r332017) @@ -67,6 +67,9 @@ struct mv_pcib_ctrl_range { uint64_t size; }; +typedef int (*get_rl_t)(device_t dev, phandle_t node, pcell_t acells, + pcell_t scells, struct resource_list *rl); + struct mv_pcib_ctrl_softc { pcell_t addr_cells; pcell_t size_cells; @@ -107,6 +110,13 @@ static device_method_t mv_pcib_ctrl_methods[] = { DEVMETHOD_END }; +static struct ofw_compat_data mv_pcib_ctrl_compat[] = { + {"mrvl,pcie-ctrl", (uintptr_t)&ofw_bus_reg_to_rl}, + {"marvell,armada-370-pcie", + (uintptr_t)&ofw_bus_assigned_addresses_to_rl}, + {NULL, (uintptr_t)NULL}, +}; + static driver_t mv_pcib_ctrl_driver = { "pcib_ctrl", mv_pcib_ctrl_methods, @@ -124,10 +134,12 @@ static int mv_pcib_ctrl_probe(device_t dev) { - if (!ofw_bus_is_compatible(dev, "mrvl,pcie-ctrl") && - !ofw_bus_is_compatible(dev, "marvell,armada-370-pcie")) + if (!ofw_bus_status_okay(dev)) return (ENXIO); + if (!ofw_bus_search_compatible(dev, mv_pcib_ctrl_compat)->ocd_data) + return (ENXIO); + device_set_desc(dev, "Marvell Integrated PCIe Bus Controller"); return (BUS_PROBE_DEFAULT); } @@ -151,6 +163,7 @@ mv_pcib_ofw_bus_attach(device_t dev) struct mv_pcib_ctrl_softc *sc; device_t child; phandle_t parent, node; + get_rl_t get_rl; parent = ofw_bus_get_node(dev); sc = device_get_softc(dev); @@ -189,8 +202,11 @@ mv_pcib_ofw_bus_attach(device_t dev) } resource_list_init(&di->di_rl); - ofw_bus_reg_to_rl(child, node, sc->addr_cells, - sc->size_cells, &di->di_rl); + get_rl = (get_rl_t) ofw_bus_search_compatible(dev, + mv_pcib_ctrl_compat)->ocd_data; + if (get_rl != NULL) + get_rl(child, node, sc->addr_cells, + sc->size_cells, &di->di_rl); device_set_ivars(child, di); } Modified: head/sys/dts/arm/armada-380.dtsi ============================================================================== --- head/sys/dts/arm/armada-380.dtsi Wed Apr 4 12:47:41 2018 (r332016) +++ head/sys/dts/arm/armada-380.dtsi Wed Apr 4 12:54:18 2018 (r332017) @@ -88,23 +88,21 @@ <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0x0 0xf1200000 MBUS_ID(0x08, 0xe8) 0xf1200000 0 0x00100000 /* Port 0 MEM */ - 0x81000000 0x0 0xf1300000 MBUS_ID(0x08, 0xe0) 0xf1300000 0 0x00100000 /* Port 0 IO */ - 0x82000000 0x0 0xf1400000 MBUS_ID(0x04, 0xe8) 0xf1400000 0 0x00100000 /* Port 1 MEM */ - 0x81000000 0x0 0xf1500000 MBUS_ID(0x04, 0xe0) 0xf1500000 0 0x00100000 /* Port 1 IO */ - 0x82000000 0x0 0xf1600000 MBUS_ID(0x04, 0xd8) 0xf1600000 0 0x00100000 /* Port 2 MEM */ - 0x81000000 0x0 0xf1700000 MBUS_ID(0x04, 0xd0) 0xf1700000 0 0x00100000 /* Port 2 IO */ - >; + 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; /* x1 port */ pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x0 0x0 0x80000 0x0 0x2000>; + reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; - #interrupt-cells = <3>; - bus-range = <0 255>; + #interrupt-cells = <1>; ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1200000 0x0 0x00100000 0x81000000 0x0 0x0 0x81000000 0x0 0xf1300000 0x0 0x00100000>; interrupt-map-mask = <0 0 0 0>; @@ -120,11 +118,10 @@ pcie@2,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0 0x0 0x40000 0x0 0x2000>; + reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; - #interrupt-cells = <3>; - bus-range = <0 255>; + #interrupt-cells = <1>; ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1400000 0x0 0x00100000 0x81000000 0x0 0x0 0x81000000 0x0 0xf1500000 0x0 0x00100000>; interrupt-map-mask = <0 0 0 0>; @@ -140,11 +137,10 @@ pcie@3,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; - reg = <0x0 0x0 0x44000 0x0 0x2000>; + reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; - #interrupt-cells = <3>; - bus-range = <0 255>; + #interrupt-cells = <1>; ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1600000 0x0 0x00100000 0x81000000 0x0 0x0 0x81000000 0x0 0xf1700000 0x0 0x00100000>; interrupt-map-mask = <0 0 0 0>; Modified: head/sys/dts/arm/armada-385.dtsi ============================================================================== --- head/sys/dts/arm/armada-385.dtsi Wed Apr 4 12:47:41 2018 (r332016) +++ head/sys/dts/arm/armada-385.dtsi Wed Apr 4 12:54:18 2018 (r332017) @@ -94,15 +94,14 @@ 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 - 0x82000000 0x0 0xf1200000 MBUS_ID(0x08, 0xe8) 0xf1200000 0 0x00100000 /* Port 0 MEM */ - 0x81000000 0x0 0xf1300000 MBUS_ID(0x08, 0xe0) 0xf1300000 0 0x00100000 /* Port 0 IO */ - 0x82000000 0x0 0xf1400000 MBUS_ID(0x04, 0xe8) 0xf1400000 0 0x00100000 /* Port 1 MEM */ - 0x81000000 0x0 0xf1500000 MBUS_ID(0x04, 0xe0) 0xf1500000 0 0x00100000 /* Port 1 IO */ - 0x82000000 0x0 0xf1600000 MBUS_ID(0x04, 0xd8) 0xf1600000 0 0x00100000 /* Port 2 MEM */ - 0x81000000 0x0 0xf1700000 MBUS_ID(0x04, 0xd0) 0xf1700000 0 0x00100000 /* Port 2 IO */ - 0x82000000 0x0 0xf1800000 MBUS_ID(0x04, 0xb8) 0xf1800000 0 0x00100000 /* Port 3 MEM */ - 0x81000000 0x0 0xf1900000 MBUS_ID(0x04, 0xb0) 0xf1900000 0 0x00100000 /* Port 3 IO */ - >; + 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ + 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ + 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; /* * This port can be either x4 or x1. When @@ -112,16 +111,14 @@ pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x0 0x0 0x80000 0x0 0x2000>; + reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; - #interrupt-cells = <3>; - bus-range = <0 255>; + #interrupt-cells = <1>; ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1200000 0x0 0x00100000 0x81000000 0x0 0x0 0x81000000 0x0 0xf1300000 0x0 0x00100000>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 8>; @@ -132,16 +129,14 @@ pcie@2,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x0 0x0 0x40000 0x0 0x2000>; + reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; - #interrupt-cells = <3>; - bus-range = <0 255>; + #interrupt-cells = <1>; ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1400000 0x0 0x00100000 0x81000000 0x0 0x0 0x81000000 0x0 0xf1500000 0x0 0x00100000>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; @@ -152,16 +147,14 @@ pcie@3,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; - reg = <0x0 0x0 0x44000 0x0 0x2000>; + reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; - #interrupt-cells = <3>; - bus-range = <0 255>; + #interrupt-cells = <1>; ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1600000 0x0 0x00100000 0x81000000 0x0 0x0 0x81000000 0x0 0xf1700000 0x0 0x00100000>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 6>; @@ -175,16 +168,14 @@ pcie@4,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; - reg = <0x0 0x0 0x48000 0x0 0x2000>; + reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; - #interrupt-cells = <3>; - bus-range = <0 255>; + #interrupt-cells = <1>; ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1800000 0x0 0x00100000 0x81000000 0x0 0x0 0x81000000 0x0 0xf1900000 0x0 0x00100000>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; marvell,pcie-port = <3>; marvell,pcie-lane = <0>; clocks = <&gateclk 7>; _______________________________________________ svn-src-all@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscr...@freebsd.org"
