Author: jhibbits
Date: Tue Oct 30 00:47:40 2018
New Revision: 339902
URL: https://svnweb.freebsd.org/changeset/base/339902

Log:
  powerpc/mpc85xx: Reset the PCIe bus on attach
  
  It seems if a Radeon card is already initialized by u-boot, it won't be
  reinitialized by the kernel, and the DRM module will fail to attach.  This
  steals the reset code from mips/octopci.c to blindly reset the bus on attach.
  This was tested on a AmigaOne X5000/20, such that it can be booted from the
  local video console, and get a video console in FreeBSD.

Modified:
  head/sys/powerpc/mpc85xx/pci_mpc85xx.c

Modified: head/sys/powerpc/mpc85xx/pci_mpc85xx.c
==============================================================================
--- head/sys/powerpc/mpc85xx/pci_mpc85xx.c      Tue Oct 30 00:23:37 2018        
(r339901)
+++ head/sys/powerpc/mpc85xx/pci_mpc85xx.c      Tue Oct 30 00:47:40 2018        
(r339902)
@@ -562,7 +562,7 @@ fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int 
        int new_pribus, new_secbus, new_subbus;
        int slot, func, maxfunc;
        uint16_t vendor, device;
-       uint8_t command, hdrtype, subclass;
+       uint8_t brctl, command, hdrtype, subclass;
 
        secbus = bus;
        for (slot = 0; slot <= maxslot; slot++) {
@@ -605,6 +605,17 @@ fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int 
                        /* Allow all DEVTYPE 1 devices */
                        if (hdrtype != PCIM_HDRTYPE_BRIDGE)
                                continue;
+
+                       brctl = fsl_pcib_read_config(sc->sc_dev, bus, slot, 
func,
+                           PCIR_BRIDGECTL_1, 1);
+                       brctl |= PCIB_BCR_SECBUS_RESET;
+                       fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
+                           PCIR_BRIDGECTL_1, brctl, 1);
+                       DELAY(100000);
+                       brctl &= ~PCIB_BCR_SECBUS_RESET;
+                       fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
+                           PCIR_BRIDGECTL_1, brctl, 1);
+                       DELAY(100000);
 
                        secbus++;
 
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