svn commit: r342652 - head/sys/arm/ti

[Ian Lepore]

Author: ian
Date: Mon Dec 31 16:01:22 2018
New Revision: 342652
URL: https://svnweb.freebsd.org/changeset/base/342652

Log:
  Support the SPI mode and bus clock frequency parameters set by the devices
  requesting SPI transfers.
  
  Reported by:  SAITOU Toshihide <to...@ruby.ocn.ne.jp>

Modified:
  head/sys/arm/ti/ti_spi.c

Modified: head/sys/arm/ti/ti_spi.c
==============================================================================
--- head/sys/arm/ti/ti_spi.c    Mon Dec 31 15:43:06 2018        (r342651)
+++ head/sys/arm/ti/ti_spi.c    Mon Dec 31 16:01:22 2018        (r342652)
@@ -446,7 +446,7 @@ ti_spi_transfer(device_t dev, device_t child, struct s
 {
        int err;
        struct ti_spi_softc *sc;
-       uint32_t reg, cs;
+       uint32_t clockhz, cs, mode, reg;
 
        sc = device_get_softc(dev);
 
@@ -457,6 +457,8 @@ ti_spi_transfer(device_t dev, device_t child, struct s
 
        /* Get the proper chip select for this child. */
        spibus_get_cs(child, &cs);
+       spibus_get_clock(child, &clockhz);
+       spibus_get_mode(child, &mode);
 
        cs &= ~SPIBUS_CS_HIGH;
 
@@ -466,6 +468,13 @@ ti_spi_transfer(device_t dev, device_t child, struct s
                return (EINVAL);
        }
 
+       if (mode > 3)
+       {
+           device_printf(dev, "Invalid mode %d requested by %s\n", mode,
+                   device_get_nameunit(child));
+           return (EINVAL);
+       }
+
        TI_SPI_LOCK(sc);
 
        /* If the controller is in use wait until it is available. */
@@ -487,8 +496,8 @@ ti_spi_transfer(device_t dev, device_t child, struct s
        /* Disable FIFO for now. */
        sc->sc_fifolvl = 1;
 
-       /* Use a safe clock - 500kHz. */
-       ti_spi_set_clock(sc, sc->sc_cs, 500000);
+       /* Set the bus frequency. */
+       ti_spi_set_clock(sc, sc->sc_cs, clockhz);
 
        /* Disable the FIFO. */
        TI_SPI_WRITE(sc, MCSPI_XFERLEVEL, 0);
@@ -500,6 +509,7 @@ ti_spi_transfer(device_t dev, device_t child, struct s
            MCSPI_CONF_DPE1 | MCSPI_CONF_DPE0 | MCSPI_CONF_DMAR |
            MCSPI_CONF_DMAW | MCSPI_CONF_EPOL);
        reg |= MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | MCSPI_CONF_WL8BITS;
+       reg |= mode; /* POL and PHA are the low bits, we can just OR-in mode */
        TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg);
 
 #if 0
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