Author: mhorne
Date: Mon Apr 29 16:16:00 2019
New Revision: 346892
URL: https://svnweb.freebsd.org/changeset/base/346892
Log:
MFC r346016:
Add option to build LLVM RISC-V target
Approved by: markj (mentor)
Added:
stable/12/tools/build/options/WITHOUT_LLVM_TARGET_RISCV
- copied unchanged from r346016,
head/tools/build/options/WITHOUT_LLVM_TARGET_RISCV
stable/12/tools/build/options/WITH_LLVM_TARGET_RISCV
- copied unchanged from r346016,
head/tools/build/options/WITH_LLVM_TARGET_RISCV
Modified:
stable/12/lib/clang/include/llvm/Config/AsmParsers.def
stable/12/lib/clang/include/llvm/Config/AsmPrinters.def
stable/12/lib/clang/include/llvm/Config/Disassemblers.def
stable/12/lib/clang/include/llvm/Config/Targets.def
stable/12/lib/clang/libllvm/Makefile
stable/12/lib/clang/llvm.build.mk
stable/12/share/man/man5/src.conf.5
stable/12/share/mk/src.opts.mk
Directory Properties:
stable/12/ (props changed)
Modified: stable/12/lib/clang/include/llvm/Config/AsmParsers.def
==============================================================================
--- stable/12/lib/clang/include/llvm/Config/AsmParsers.def Mon Apr 29
16:14:24 2019 (r346891)
+++ stable/12/lib/clang/include/llvm/Config/AsmParsers.def Mon Apr 29
16:16:00 2019 (r346892)
@@ -19,6 +19,9 @@ LLVM_ASM_PARSER(Mips)
#ifdef LLVM_TARGET_ENABLE_POWERPC
LLVM_ASM_PARSER(PowerPC)
#endif
+#ifdef LLVM_TARGET_ENABLE_RISCV
+LLVM_ASM_PARSER(RISCV)
+#endif
#ifdef LLVM_TARGET_ENABLE_SPARC
LLVM_ASM_PARSER(Sparc)
#endif
Modified: stable/12/lib/clang/include/llvm/Config/AsmPrinters.def
==============================================================================
--- stable/12/lib/clang/include/llvm/Config/AsmPrinters.def Mon Apr 29
16:14:24 2019 (r346891)
+++ stable/12/lib/clang/include/llvm/Config/AsmPrinters.def Mon Apr 29
16:16:00 2019 (r346892)
@@ -19,6 +19,9 @@ LLVM_ASM_PRINTER(Mips)
#ifdef LLVM_TARGET_ENABLE_POWERPC
LLVM_ASM_PRINTER(PowerPC)
#endif
+#ifdef LLVM_TARGET_ENABLE_RISCV
+LLVM_ASM_PRINTER(RISCV)
+#endif
#ifdef LLVM_TARGET_ENABLE_SPARC
LLVM_ASM_PRINTER(Sparc)
#endif
Modified: stable/12/lib/clang/include/llvm/Config/Disassemblers.def
==============================================================================
--- stable/12/lib/clang/include/llvm/Config/Disassemblers.def Mon Apr 29
16:14:24 2019 (r346891)
+++ stable/12/lib/clang/include/llvm/Config/Disassemblers.def Mon Apr 29
16:16:00 2019 (r346892)
@@ -19,6 +19,9 @@ LLVM_DISASSEMBLER(Mips)
#ifdef LLVM_TARGET_ENABLE_POWERPC
LLVM_DISASSEMBLER(PowerPC)
#endif
+#ifdef LLVM_TARGET_ENABLE_RISCV
+LLVM_DISASSEMBLER(RISCV)
+#endif
#ifdef LLVM_TARGET_ENABLE_SPARC
LLVM_DISASSEMBLER(Sparc)
#endif
Modified: stable/12/lib/clang/include/llvm/Config/Targets.def
==============================================================================
--- stable/12/lib/clang/include/llvm/Config/Targets.def Mon Apr 29 16:14:24
2019 (r346891)
+++ stable/12/lib/clang/include/llvm/Config/Targets.def Mon Apr 29 16:16:00
2019 (r346892)
@@ -19,6 +19,9 @@ LLVM_TARGET(Mips)
#ifdef LLVM_TARGET_ENABLE_POWERPC
LLVM_TARGET(PowerPC)
#endif
+#ifdef LLVM_TARGET_ENABLE_RISCV
+LLVM_TARGET(RISCV)
+#endif
#ifdef LLVM_TARGET_ENABLE_SPARC
LLVM_TARGET(Sparc)
#endif
Modified: stable/12/lib/clang/libllvm/Makefile
==============================================================================
--- stable/12/lib/clang/libllvm/Makefile Mon Apr 29 16:14:24 2019
(r346891)
+++ stable/12/lib/clang/libllvm/Makefile Mon Apr 29 16:16:00 2019
(r346892)
@@ -10,14 +10,15 @@ CFLAGS+= -I${.OBJDIR}
.if ${MK_LLVM_TARGET_AARCH64} == "no" && ${MK_LLVM_TARGET_ARM} == "no" && \
${MK_LLVM_TARGET_BPF} == "no" && ${MK_LLVM_TARGET_MIPS} == "no" && \
- ${MK_LLVM_TARGET_POWERPC} == "no" && ${MK_LLVM_TARGET_SPARC} == "no" && \
- ${MK_LLVM_TARGET_X86} == "no"
+ ${MK_LLVM_TARGET_POWERPC} == "no" && ${MK_LLVM_TARGET_RISCV} == "no" && \
+ ${MK_LLVM_TARGET_SPARC} == "no" && ${MK_LLVM_TARGET_X86} == "no"
.error Please enable at least one of: MK_LLVM_TARGET_AARCH64,\
MK_LLVM_TARGET_ARM, MK_LLVM_TARGET_BPF, MK_LLVM_TARGET_MIPS, \
- MK_LLVM_TARGET_POWERPC, MK_LLVM_TARGET_SPARC, or MK_LLVM_TARGET_X86
+ MK_LLVM_TARGET_POWERPC, MK_LLVM_TARGET_RISCV, MK_LLVM_TARGET_SPARC, \
+ or MK_LLVM_TARGET_X86
.endif
-.for arch in AArch64 ARM BPF Mips PowerPC Sparc X86
+.for arch in AArch64 ARM BPF Mips PowerPC RISCV Sparc X86
. if ${MK_LLVM_TARGET_${arch:tu}} != "no"
CFLAGS+= -I${LLVM_SRCS}/lib/Target/${arch}
. endif
@@ -1128,6 +1129,34 @@ SRCS_MIN+= Target/PowerPC/PPCVSXFMAMutate.cpp
SRCS_MIN+= Target/PowerPC/PPCVSXSwapRemoval.cpp
SRCS_MIN+= Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp
.endif # MK_LLVM_TARGET_POWERPC
+.if ${MK_LLVM_TARGET_RISCV} != "no"
+SRCS_MIN+= Target/RISCV/AsmParser/RISCVAsmParser.cpp
+SRCS_MIN+= Target/RISCV/Disassembler/RISCVDisassembler.cpp
+SRCS_MIN+= Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
+SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
+SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
+SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
+SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+SRCS_MIN+= Target/RISCV/RISCVAsmPrinter.cpp
+SRCS_MIN+= Target/RISCV/RISCVExpandPseudoInsts.cpp
+SRCS_MIN+= Target/RISCV/RISCVFrameLowering.cpp
+SRCS_MIN+= Target/RISCV/RISCVInstrInfo.cpp
+SRCS_MIN+= Target/RISCV/RISCVISelDAGToDAG.cpp
+SRCS_MIN+= Target/RISCV/RISCVISelLowering.cpp
+SRCS_MIN+= Target/RISCV/RISCVMCInstLower.cpp
+SRCS_MIN+= Target/RISCV/RISCVMergeBaseOffset.cpp
+SRCS_MIN+= Target/RISCV/RISCVRegisterInfo.cpp
+SRCS_MIN+= Target/RISCV/RISCVSubtarget.cpp
+SRCS_MIN+= Target/RISCV/RISCVTargetMachine.cpp
+SRCS_MIN+= Target/RISCV/RISCVTargetObjectFile.cpp
+SRCS_MIN+= Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
+SRCS_MIN+= Target/RISCV/Utils/RISCVBaseInfo.cpp
+SRCS_MIN+= Target/RISCV/Utils/RISCVMatInt.cpp
+.endif # MK_LLVM_TARGET_RISCV
.if ${MK_LLVM_TARGET_SPARC} != "no"
SRCS_MIN+= Target/Sparc/AsmParser/SparcAsmParser.cpp
SRCS_MIN+= Target/Sparc/DelaySlotFiller.cpp
@@ -1545,13 +1574,15 @@ beforebuild:
# Note: some rules are superfluous, not every combination is valid.
.for arch in \
- AArch64/AArch64 ARM/ARM BPF/BPF Mips/Mips PowerPC/PPC Sparc/Sparc
X86/X86
+ AArch64/AArch64 ARM/ARM BPF/BPF Mips/Mips PowerPC/PPC Sparc/Sparc \
+ RISCV/RISCV X86/X86
. for hdr in \
AsmMatcher/-gen-asm-matcher \
AsmWriter1/-gen-asm-writer,-asmwriternum=1 \
AsmWriter/-gen-asm-writer \
CallingConv/-gen-callingconv \
CodeEmitter/-gen-emitter \
+ CompressInstEmitter/-gen-compress-inst-emitter \
DAGISel/-gen-dag-isel \
DisassemblerTables/-gen-disassembler \
EVEX2VEXTables/-gen-x86-EVEX2VEX-tables \
@@ -1643,6 +1674,21 @@ TGHDRS+= PPCGenMCCodeEmitter.inc
TGHDRS+= PPCGenRegisterInfo.inc
TGHDRS+= PPCGenSubtargetInfo.inc
.endif # MK_LLVM_TARGET_POWERPC
+.if ${MK_LLVM_TARGET_RISCV} != "no"
+TGHDRS+= RISCVGenAsmMatcher.inc
+TGHDRS+= RISCVGenAsmWriter.inc
+TGHDRS+= RISCVGenCallingConv.inc
+TGHDRS+= RISCVGenCompressInstEmitter.inc
+TGHDRS+= RISCVGenDAGISel.inc
+TGHDRS+= RISCVGenDisassemblerTables.inc
+TGHDRS+= RISCVGenDAGISel.inc
+TGHDRS+= RISCVGenInstrInfo.inc
+TGHDRS+= RISCVGenMCCodeEmitter.inc
+TGHDRS+= RISCVGenMCPseudoLowering.inc
+TGHDRS+= RISCVGenRegisterInfo.inc
+TGHDRS+= RISCVGenSubtargetInfo.inc
+TGHDRS+= RISCVGenSystemOperands.inc
+.endif # MK_LLVM_TARGET_RISCV
.if ${MK_LLVM_TARGET_SPARC} != "no"
TGHDRS+= SparcGenAsmMatcher.inc
TGHDRS+= SparcGenAsmWriter.inc
Modified: stable/12/lib/clang/llvm.build.mk
==============================================================================
--- stable/12/lib/clang/llvm.build.mk Mon Apr 29 16:14:24 2019
(r346891)
+++ stable/12/lib/clang/llvm.build.mk Mon Apr 29 16:16:00 2019
(r346892)
@@ -69,6 +69,12 @@ CFLAGS+= -DLLVM_TARGET_ENABLE_POWERPC
LLVM_NATIVE_ARCH= PowerPC
. endif
.endif
+.if ${MK_LLVM_TARGET_RISCV} != "no"
+CFLAGS+= -DLLVM_TARGET_ENABLE_RISCV
+. if ${MACHINE_CPUARCH} == "riscv"
+LLVM_NATIVE_ARCH= RISCV
+. endif
+.endif
.if ${MK_LLVM_TARGET_SPARC} != "no"
CFLAGS+= -DLLVM_TARGET_ENABLE_SPARC
. if ${MACHINE_CPUARCH} == "sparc64"
Modified: stable/12/share/man/man5/src.conf.5
==============================================================================
--- stable/12/share/man/man5/src.conf.5 Mon Apr 29 16:14:24 2019
(r346891)
+++ stable/12/share/man/man5/src.conf.5 Mon Apr 29 16:16:00 2019
(r346892)
@@ -1,6 +1,6 @@
.\" DO NOT EDIT-- this file is @generated by tools/build/options/makeman.
.\" $FreeBSD$
-.Dd April 17, 2019
+.Dd March 29, 2019
.Dt SRC.CONF 5
.Os
.Sh NAME
@@ -151,6 +151,10 @@ for Verified Exec and
When set, these options are also in effect:
.Pp
.Bl -inset -compact
+.It Va WITH_LOADER_EFI_SECUREBOOT
+(unless
+.Va WITHOUT_LOADER_EFI_SECUREBOOT
+is set explicitly)
.It Va WITH_LOADER_VERIEXEC
(unless
.Va WITHOUT_LOADER_VERIEXEC
@@ -380,6 +384,10 @@ is set explicitly)
(unless
.Va WITH_LLVM_TARGET_POWERPC
is set explicitly)
+.It Va WITHOUT_LLVM_TARGET_RISCV
+(unless
+.Va WITH_LLVM_TARGET_RISCV
+is set explicitly)
.It Va WITHOUT_LLVM_TARGET_SPARC
(unless
.Va WITH_LLVM_TARGET_SPARC
@@ -1190,6 +1198,20 @@ option should be used rather than this in most cases.
.Pp
This is a default setting on
amd64/amd64, arm/armv7, arm64/aarch64, i386/i386, mips/mipsel, mips/mips,
mips/mips64el, mips/mips64, mips/mipsn32, mips/mipselhf, mips/mipshf,
mips/mips64elhf, mips/mips64hf, powerpc/powerpc, powerpc/powerpc64 and
powerpc/powerpcspe.
+.It Va WITHOUT_LLVM_TARGET_RISCV
+Set to not build LLVM target support for RISC-V.
+The
+.Va LLVM_TARGET_ALL
+option should be used rather than this in most cases.
+.Pp
+This is a default setting on
+amd64/amd64, arm/arm, arm/armv6, arm/armv7, arm64/aarch64, i386/i386,
mips/mipsel, mips/mips, mips/mips64el, mips/mips64, mips/mipsn32,
mips/mipselhf, mips/mipshf, mips/mips64elhf, mips/mips64hf, powerpc/powerpc,
powerpc/powerpc64, powerpc/powerpcspe, and sparc/sparc64.
+.It Va WITH_LLVM_TARGET_RISCV
+Set to build LLVM target support for RISC-V.
+The
+.Va LLVM_TARGET_ALL
+option should be used rather than this in most cases.
+.Pp
.It Va WITHOUT_LLVM_TARGET_SPARC
Set to not build LLVM target support for SPARC.
The
@@ -1222,6 +1244,11 @@ option should be used rather than this in most cases.
.Pp
This is a default setting on
amd64/amd64, arm/armv7, arm64/aarch64, i386/i386, mips/mipsel, mips/mips,
mips/mips64el, mips/mips64, mips/mipsn32, mips/mipselhf, mips/mipshf,
mips/mips64elhf, mips/mips64hf, powerpc/powerpc, powerpc/powerpc64 and
powerpc/powerpcspe.
+.It Va WITH_LOADER_EFI_SECUREBOOT
+Enable building
+.Xr loader 8
+with support for verification based on certificates obtained from UEFI.
+.Pp
.It Va WITH_LOADER_FIREWIRE
Enable firewire support in /boot/loader on x86. This option is a nop
on all other platforms.
@@ -1262,6 +1289,14 @@ with support for verifcation similar to Verified Exec.
.Pp
It depends on
.Va WITH_BEARSSL
+When set, these options are also in effect:
+.Pp
+.Bl -inset -compact
+.It Va WITH_LOADER_EFI_SECUREBOOT
+(unless
+.Va WITHOUT_LOADER_EFI_SECUREBOOT
+is set explicitly)
+.El
.It Va WITHOUT_LOADER_ZFS
Set to not build ZFS file system boot loader support.
.It Va WITHOUT_LOCALES
Modified: stable/12/share/mk/src.opts.mk
==============================================================================
--- stable/12/share/mk/src.opts.mk Mon Apr 29 16:14:24 2019
(r346891)
+++ stable/12/share/mk/src.opts.mk Mon Apr 29 16:16:00 2019
(r346892)
@@ -285,6 +285,7 @@ __DEFAULT_DEPENDENT_OPTIONS+= LLVM_TARGET_${__llt:${__
.endfor
__DEFAULT_NO_OPTIONS+=LLVM_TARGET_BPF
+__DEFAULT_NO_OPTIONS+=LLVM_TARGET_RISCV
.include <bsd.compiler.mk>
# If the compiler is not C++11 capable, disable Clang and use GCC instead.
Copied: stable/12/tools/build/options/WITHOUT_LLVM_TARGET_RISCV (from r346016,
head/tools/build/options/WITHOUT_LLVM_TARGET_RISCV)
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ stable/12/tools/build/options/WITHOUT_LLVM_TARGET_RISCV Mon Apr 29
16:16:00 2019 (r346892, copy of r346016,
head/tools/build/options/WITHOUT_LLVM_TARGET_RISCV)
@@ -0,0 +1,5 @@
+.\" $FreeBSD$
+Set to not build LLVM target support for RISC-V.
+The
+.Va LLVM_TARGET_ALL
+option should be used rather than this in most cases.
Copied: stable/12/tools/build/options/WITH_LLVM_TARGET_RISCV (from r346016,
head/tools/build/options/WITH_LLVM_TARGET_RISCV)
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ stable/12/tools/build/options/WITH_LLVM_TARGET_RISCV Mon Apr 29
16:16:00 2019 (r346892, copy of r346016,
head/tools/build/options/WITH_LLVM_TARGET_RISCV)
@@ -0,0 +1,5 @@
+.\" $FreeBSD$
+Set to build LLVM target support for RISC-V.
+The
+.Va LLVM_TARGET_ALL
+option should be used rather than this in most cases.
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