Author: hselasky
Date: Thu May 16 18:19:08 2019
New Revision: 347868
URL: https://svnweb.freebsd.org/changeset/base/347868
Log:
MFC r347312:
Add Firmware Reset Level, MFRL, register accessors in mlx5core.
Submitted by: kib@
Sponsored by: Mellanox Technologies
Modified:
stable/11/sys/dev/mlx5/device.h
stable/11/sys/dev/mlx5/driver.h
stable/11/sys/dev/mlx5/mlx5_core/mlx5_core.h
stable/11/sys/dev/mlx5/mlx5_core/mlx5_port.c
stable/11/sys/dev/mlx5/mlx5_ifc.h
Directory Properties:
stable/11/ (props changed)
Modified: stable/11/sys/dev/mlx5/device.h
==============================================================================
--- stable/11/sys/dev/mlx5/device.h Thu May 16 18:18:22 2019
(r347867)
+++ stable/11/sys/dev/mlx5/device.h Thu May 16 18:19:08 2019
(r347868)
@@ -1216,6 +1216,11 @@ enum {
MLX5_GEN_EVENT_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5,
};
+enum {
+ MLX5_FRL_LEVEL3 = 0x8,
+ MLX5_FRL_LEVEL6 = 0x40,
+};
+
/* 8 regular priorities + 1 for multicast */
#define MLX5_NUM_BYPASS_FTS 9
Modified: stable/11/sys/dev/mlx5/driver.h
==============================================================================
--- stable/11/sys/dev/mlx5/driver.h Thu May 16 18:18:22 2019
(r347867)
+++ stable/11/sys/dev/mlx5/driver.h Thu May 16 18:19:08 2019
(r347868)
@@ -152,6 +152,7 @@ enum {
MLX5_REG_HOST_ENDIANNESS = 0x7004,
MLX5_REG_MTMP = 0x900a,
MLX5_REG_MCIA = 0x9014,
+ MLX5_REG_MFRL = 0x9028,
MLX5_REG_MPCNT = 0x9051,
MLX5_REG_MCQI = 0x9061,
MLX5_REG_MCC = 0x9062,
Modified: stable/11/sys/dev/mlx5/mlx5_core/mlx5_core.h
==============================================================================
--- stable/11/sys/dev/mlx5/mlx5_core/mlx5_core.h Thu May 16 18:18:22
2019 (r347867)
+++ stable/11/sys/dev/mlx5/mlx5_core/mlx5_core.h Thu May 16 18:19:08
2019 (r347868)
@@ -82,6 +82,8 @@ int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32
u8 feature_group, u8 access_reg_group);
int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap,
u8 feature_group, u8 access_reg_group);
+int mlx5_query_mfrl_reg(struct mlx5_core_dev *mdev, u8 *reset_level);
+int mlx5_set_mfrl_reg(struct mlx5_core_dev *mdev, u8 reset_level);
int mlx5_cmd_init_hca(struct mlx5_core_dev *dev);
int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);
Modified: stable/11/sys/dev/mlx5/mlx5_core/mlx5_port.c
==============================================================================
--- stable/11/sys/dev/mlx5/mlx5_core/mlx5_port.c Thu May 16 18:18:22
2019 (r347867)
+++ stable/11/sys/dev/mlx5/mlx5_core/mlx5_port.c Thu May 16 18:19:08
2019 (r347868)
@@ -1210,3 +1210,29 @@ int mlx5_query_pddr_range_info(struct mlx5_core_dev *m
return (0);
}
EXPORT_SYMBOL_GPL(mlx5_query_pddr_range_info);
+
+int
+mlx5_query_mfrl_reg(struct mlx5_core_dev *mdev, u8 *reset_level)
+{
+ u32 mfrl[MLX5_ST_SZ_DW(mfrl_reg)] = {};
+ int sz = MLX5_ST_SZ_BYTES(mfrl_reg);
+ int err;
+
+ err = mlx5_core_access_reg(mdev, mfrl, sz, mfrl, sz, MLX5_REG_MFRL,
+ 0, 0);
+ if (err == 0)
+ *reset_level = MLX5_GET(mfrl_reg, mfrl, reset_level);
+ return (err);
+}
+
+int
+mlx5_set_mfrl_reg(struct mlx5_core_dev *mdev, u8 reset_level)
+{
+ u32 mfrl[MLX5_ST_SZ_DW(mfrl_reg)] = {};
+ int sz = MLX5_ST_SZ_BYTES(mfrl_reg);
+
+ MLX5_SET(mfrl_reg, mfrl, reset_level, reset_level);
+
+ return (mlx5_core_access_reg(mdev, mfrl, sz, mfrl, sz, MLX5_REG_MFRL,
+ 0, 1));
+}
Modified: stable/11/sys/dev/mlx5/mlx5_ifc.h
==============================================================================
--- stable/11/sys/dev/mlx5/mlx5_ifc.h Thu May 16 18:18:22 2019
(r347867)
+++ stable/11/sys/dev/mlx5/mlx5_ifc.h Thu May 16 18:19:08 2019
(r347868)
@@ -10409,4 +10409,9 @@ struct mlx5_ifc_qpts_reg_bits {
u8 trust_state[0x3];
};
+struct mlx5_ifc_mfrl_reg_bits {
+ u8 reserved_at_0[0x38];
+ u8 reset_level[0x8];
+};
+
#endif /* MLX5_IFC_H */
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