On Fri, Jun 28, 2019 at 12:45 PM John Baldwin <j...@freebsd.org> wrote: > > On 6/27/19 5:10 PM, Mitchell Horne wrote: > > Author: mhorne > > Date: Fri Jun 28 00:10:26 2019 > > New Revision: 349482 > > URL: https://svnweb.freebsd.org/changeset/base/349482 > > > > Log: > > readelf: Add support for RISC-V specific e_flags > > > > Reviewed by: markj > > Approved by: markj (mentor) > > MFC after: 3 days > > Differential Revision: https://reviews.freebsd.org/D20767 > > > > Modified: > > head/contrib/elftoolchain/common/elfdefinitions.h > > head/contrib/elftoolchain/readelf/readelf.c > > > > Modified: head/contrib/elftoolchain/common/elfdefinitions.h > > ============================================================================== > > --- head/contrib/elftoolchain/common/elfdefinitions.h Fri Jun 28 00:03:29 > > 2019 (r349481) > > +++ head/contrib/elftoolchain/common/elfdefinitions.h Fri Jun 28 00:10:26 > > 2019 (r349482) > > @@ -426,6 +426,22 @@ _ELF_DEFINE_EF(EF_PPC_RELOCATABLE, 0x00010000UL, > > \ > > "-mrelocatable flag") \ > > _ELF_DEFINE_EF(EF_PPC_RELOCATABLE_LIB, 0x00008000UL, \ > > "-mrelocatable-lib flag") \ > > +_ELF_DEFINE_EF(EF_RISCV_RVE, 0x00000008UL, \ > > + "Compressed instruction ABI") \ > > I don't think this description for RVE is quite right. RVE is for RV32E which > is not using compressed ('C') instructions, but using a smaller register file > (16 GPRs instead of 32) which is in theory intended for embedded / > microprocessor > variants. The riscv-elf-psabi-doc describes it as: > > EF_RISCV_RVE (0x0008): This bit is set when the binary targets the E ABI. >
Yep, good catch. This got duplicated from the RVC entry and slipped by during review. I'll adjust it. Mitchell > -- > John Baldwin _______________________________________________ svn-src-all@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscr...@freebsd.org"
