Author: yongari
Date: Mon Oct  4 18:09:01 2010
New Revision: 213411
URL: http://svn.freebsd.org/changeset/base/213411

Log:
  Enable fix for read DMA FIFO overruns on controllers that have this
  fix. Note, we still need workaround for controllers that lacks this
  fix and it needs more work in RX BD updating.
  
  Submitted by: davidch

Modified:
  head/sys/dev/bge/if_bge.c
  head/sys/dev/bge/if_bgereg.h

Modified: head/sys/dev/bge/if_bge.c
==============================================================================
--- head/sys/dev/bge/if_bge.c   Mon Oct  4 18:01:23 2010        (r213410)
+++ head/sys/dev/bge/if_bge.c   Mon Oct  4 18:09:01 2010        (r213411)
@@ -1858,6 +1858,19 @@ bge_blockinit(struct bge_softc *sc)
                    sc->bge_asicrev == BGE_ASICREV_BCM57780)
                        val |= BGE_RDMAMODE_TSO6_ENABLE;
        }
+       if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
+           sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
+           sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
+           sc->bge_asicrev == BGE_ASICREV_BCM57780) {
+               /*
+                * Enable fix for read DMA FIFO overruns.
+                * The fix is to limit the number of RX BDs
+                * the hardware would fetch at a fime.
+                */
+               CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
+                   CSR_READ_4(sc, BGE_RDMA_RSRVCTRL) |
+                   BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
+       }
        CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
        DELAY(40);
 

Modified: head/sys/dev/bge/if_bgereg.h
==============================================================================
--- head/sys/dev/bge/if_bgereg.h        Mon Oct  4 18:01:23 2010        
(r213410)
+++ head/sys/dev/bge/if_bgereg.h        Mon Oct  4 18:09:01 2010        
(r213411)
@@ -1431,6 +1431,7 @@
  */
 #define        BGE_RDMA_MODE                   0x4800
 #define        BGE_RDMA_STATUS                 0x4804
+#define        BGE_RDMA_RSRVCTRL               0x4900
 
 /* Read DMA mode register */
 #define        BGE_RDMAMODE_RESET              0x00000001
@@ -1462,6 +1463,9 @@
 #define        BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
 #define        BGE_RDMASTAT_LOCWRITE_TOOBIG    0x00000200
 
+/* Read DMA Reserved Control register */
+#define        BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
+
 /*
  * Write DMA control registers
  */
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