Author: brooks
Date: Wed Jan 29 22:01:42 2014
New Revision: 261277
URL: http://svnweb.freebsd.org/changeset/base/261277
Log:
MFC r256937:
MFP4:
Change 231031 by brooks@brooks_zenith on 2013/07/11 16:22:08
Turn the unused and uncompilable MIPS_DISABLE_L1_CACHE define in
cache.c into an option and when set force I- and D-cache line
sizes to 0 (the latter part might be better as a tunable).
Fix some casts in an #if 0'd bit of code which attempts to
disable L1 cache ops when the cache is coherent.
Sponsored by: DARPA/AFRL
Modified:
stable/10/sys/conf/options.mips
stable/10/sys/mips/mips/cache.c
stable/10/sys/mips/mips/cpu.c
Directory Properties:
stable/10/ (props changed)
Modified: stable/10/sys/conf/options.mips
==============================================================================
--- stable/10/sys/conf/options.mips Wed Jan 29 21:57:00 2014
(r261276)
+++ stable/10/sys/conf/options.mips Wed Jan 29 22:01:42 2014
(r261277)
@@ -71,6 +71,11 @@ TICK_USE_MALTA_RTC opt_global.h
MAXMEM opt_global.h
#
+# Manual override of cache config
+#
+MIPS_DISABLE_L1_CACHE opt_global.h
+
+#
# Options that control the Cavium Simple Executive.
#
OCTEON_MODEL opt_cvmx.h
Modified: stable/10/sys/mips/mips/cache.c
==============================================================================
--- stable/10/sys/mips/mips/cache.c Wed Jan 29 21:57:00 2014
(r261276)
+++ stable/10/sys/mips/mips/cache.c Wed Jan 29 22:01:42 2014
(r261277)
@@ -116,11 +116,9 @@ mips_config_cache(struct mips_cpuinfo *
#ifdef MIPS_DISABLE_L1_CACHE
case 0:
- mips_cache_ops.mco_icache_sync_all = cache_noop;
- mips_cache_ops.mco_icache_sync_range =
- (void (*)(vaddr_t, vsize_t))cache_noop;
- mips_cache_ops.mco_icache_sync_range_index =
- (void (*)(vaddr_t, vsize_t))cache_noop;
+ mips_cache_ops.mco_icache_sync_all = (void (*)(void))cache_noop;
+ mips_cache_ops.mco_icache_sync_range = cache_noop;
+ mips_cache_ops.mco_icache_sync_range_index = cache_noop;
break;
#endif
default:
@@ -193,20 +191,16 @@ mips_config_cache(struct mips_cpuinfo *
#endif
#ifdef MIPS_DISABLE_L1_CACHE
case 0:
- mips_cache_ops.mco_pdcache_wbinv_all = cache_noop;
- mips_cache_ops.mco_intern_pdcache_wbinv_all = cache_noop;
- mips_cache_ops.mco_pdcache_wbinv_range =
- (void (*)(vaddr_t, vsize_t))cache_noop;
- mips_cache_ops.mco_pdcache_wbinv_range_index =
- (void (*)(vaddr_t, vsize_t))cache_noop;
+ mips_cache_ops.mco_pdcache_wbinv_all =
+ mips_cache_ops.mco_intern_pdcache_wbinv_all =
+ (void (*)(void))cache_noop;
+ mips_cache_ops.mco_pdcache_wbinv_range = cache_noop;
+ mips_cache_ops.mco_pdcache_wbinv_range_index = cache_noop;
mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
- (void (*)(vaddr_t, vsize_t))cache_noop;
- mips_cache_ops.mco_pdcache_inv_range =
- (void (*)(vaddr_t, vsize_t))cache_noop;
- mips_cache_ops.mco_pdcache_wb_range =
- (void (*)(vaddr_t, vsize_t))cache_noop;
- mips_cache_ops.mco_intern_pdcache_wb_range =
- (void (*)(vaddr_t, vsize_t))cache_noop;
+ cache_noop;
+ mips_cache_ops.mco_pdcache_inv_range = cache_noop;
+ mips_cache_ops.mco_pdcache_wb_range = cache_noop;
+ mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop;
break;
#endif
default:
@@ -222,26 +216,22 @@ mips_config_cache(struct mips_cpuinfo *
#ifdef CACHE_DEBUG
printf(" Dcache is coherent\n");
#endif
- mips_cache_ops.mco_pdcache_wbinv_all = cache_noop;
- mips_cache_ops.mco_pdcache_wbinv_range =
- (void (*)(vaddr_t, vsize_t))cache_noop;
- mips_cache_ops.mco_pdcache_wbinv_range_index =
- (void (*)(vaddr_t, vsize_t))cache_noop;
- mips_cache_ops.mco_pdcache_inv_range =
- (void (*)(vaddr_t, vsize_t))cache_noop;
- mips_cache_ops.mco_pdcache_wb_range =
- (void (*)(vaddr_t, vsize_t))cache_noop;
+ mips_cache_ops.mco_pdcache_wbinv_all =
+ (void (*)(void))cache_noop;
+ mips_cache_ops.mco_pdcache_wbinv_range = cache_noop;
+ mips_cache_ops.mco_pdcache_wbinv_range_index = cache_noop;
+ mips_cache_ops.mco_pdcache_inv_range = cache_noop;
+ mips_cache_ops.mco_pdcache_wb_range = cache_noop;
}
if (mips_cpu_flags & CPU_MIPS_I_D_CACHE_COHERENT) {
#ifdef CACHE_DEBUG
printf(" Icache is coherent against Dcache\n");
#endif
mips_cache_ops.mco_intern_pdcache_wbinv_all =
- cache_noop;
+ (void (*)(void))cache_noop;
mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
- (void (*)(vaddr_t, vsize_t))cache_noop;
- mips_cache_ops.mco_intern_pdcache_wb_range =
- (void (*)(vaddr_t, vsize_t))cache_noop;
+ cache_noop;
+ mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop;
}
#endif
Modified: stable/10/sys/mips/mips/cpu.c
==============================================================================
--- stable/10/sys/mips/mips/cpu.c Wed Jan 29 21:57:00 2014
(r261276)
+++ stable/10/sys/mips/mips/cpu.c Wed Jan 29 22:01:42 2014
(r261277)
@@ -128,6 +128,9 @@ mips_get_identity(struct mips_cpuinfo *c
#endif
/* L1 instruction cache. */
+#ifdef MIPS_DISABLE_L1_CACHE
+ cpuinfo->l1.ic_linesize = 0;
+#else
tmp = (cfg1 & MIPS_CONFIG1_IL_MASK) >> MIPS_CONFIG1_IL_SHIFT;
if (tmp != 0) {
cpuinfo->l1.ic_linesize = 1 << (tmp + 1);
@@ -135,8 +138,12 @@ mips_get_identity(struct mips_cpuinfo *c
cpuinfo->l1.ic_nsets =
1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >>
MIPS_CONFIG1_IS_SHIFT) + 6);
}
+#endif
/* L1 data cache. */
+#ifdef MIPS_DISABLE_L1_CACHE
+ cpuinfo->l1.dc_linesize = 0;
+#else
#ifndef CPU_CNMIPS
tmp = (cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT;
if (tmp != 0) {
@@ -173,6 +180,7 @@ mips_get_identity(struct mips_cpuinfo *c
/* All Octeon models use 128 byte line size. */
cpuinfo->l1.dc_linesize = 128;
#endif
+#endif
cpuinfo->l1.ic_size = cpuinfo->l1.ic_linesize
* cpuinfo->l1.ic_nsets * cpuinfo->l1.ic_nways;
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