Author: dim Date: Mon May 12 18:45:56 2014 New Revision: 265925 URL: http://svnweb.freebsd.org/changeset/base/265925
Log: Upgrade our copy of llvm/clang to 3.4.1 release. This release contains mostly fixes, for the following upstream bugs: http://llvm.org/PR16365 http://llvm.org/PR17473 http://llvm.org/PR18000 http://llvm.org/PR18068 http://llvm.org/PR18102 http://llvm.org/PR18165 http://llvm.org/PR18260 http://llvm.org/PR18290 http://llvm.org/PR18316 http://llvm.org/PR18460 http://llvm.org/PR18473 http://llvm.org/PR18515 http://llvm.org/PR18526 http://llvm.org/PR18600 http://llvm.org/PR18762 http://llvm.org/PR18773 http://llvm.org/PR18860 http://llvm.org/PR18994 http://llvm.org/PR19007 http://llvm.org/PR19010 http://llvm.org/PR19033 http://llvm.org/PR19059 http://llvm.org/PR19144 http://llvm.org/PR19326 MFC after: 2 weeks Deleted: head/contrib/llvm/patches/patch-r262809-clang-r203007-destructor-calling-conv.diff Modified: head/ObsoleteFiles.inc head/UPDATING head/contrib/llvm/include/llvm/IR/IntrinsicsX86.td head/contrib/llvm/include/llvm/MC/MCAsmInfo.h head/contrib/llvm/lib/Analysis/BasicAliasAnalysis.cpp head/contrib/llvm/lib/Analysis/IVUsers.cpp head/contrib/llvm/lib/Analysis/ScalarEvolution.cpp head/contrib/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp head/contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp head/contrib/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp head/contrib/llvm/lib/MC/MCAsmInfo.cpp head/contrib/llvm/lib/MC/MCAsmInfoCOFF.cpp head/contrib/llvm/lib/MC/MCAsmInfoDarwin.cpp head/contrib/llvm/lib/MC/MCDwarf.cpp head/contrib/llvm/lib/MC/MCParser/AsmParser.cpp head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp head/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.td head/contrib/llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp head/contrib/llvm/lib/Target/AArch64/AArch64TargetObjectFile.h head/contrib/llvm/lib/Target/ARM/A15SDOptimizer.cpp head/contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp head/contrib/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp head/contrib/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp head/contrib/llvm/lib/Target/ARM/ARMInstrNEON.td head/contrib/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp head/contrib/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h head/contrib/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp head/contrib/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp head/contrib/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp head/contrib/llvm/lib/Target/PowerPC/PPCFastISel.cpp head/contrib/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp head/contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp head/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp head/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.td head/contrib/llvm/lib/Target/PowerPC/PPCRegisterInfo.td head/contrib/llvm/lib/Target/PowerPC/PPCSubtarget.h head/contrib/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp head/contrib/llvm/lib/Target/R600/AMDGPUISelLowering.cpp head/contrib/llvm/lib/Target/R600/AMDGPUInstructions.td head/contrib/llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCAsmInfo.cpp head/contrib/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp head/contrib/llvm/lib/Target/R600/R600InstrInfo.cpp head/contrib/llvm/lib/Target/R600/R600Instructions.td head/contrib/llvm/lib/Target/R600/SIFixSGPRCopies.cpp head/contrib/llvm/lib/Target/R600/SIInsertWaits.cpp head/contrib/llvm/lib/Target/R600/SIInstrInfo.td head/contrib/llvm/lib/Target/R600/SIInstructions.td head/contrib/llvm/lib/Target/R600/SIIntrinsics.td head/contrib/llvm/lib/Target/R600/SILowerControlFlow.cpp head/contrib/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp head/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c head/contrib/llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp head/contrib/llvm/lib/Target/X86/X86AsmPrinter.cpp head/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp head/contrib/llvm/lib/Target/X86/X86InstrCompiler.td head/contrib/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp head/contrib/llvm/lib/Transforms/Scalar/LoopRerollPass.cpp head/contrib/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp head/contrib/llvm/lib/Transforms/Utils/LCSSA.cpp head/contrib/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp head/contrib/llvm/tools/clang/include/clang/Driver/Driver.h head/contrib/llvm/tools/clang/include/clang/Driver/ToolChain.h head/contrib/llvm/tools/clang/lib/AST/ASTDumper.cpp head/contrib/llvm/tools/clang/lib/AST/ExprConstant.cpp head/contrib/llvm/tools/clang/lib/AST/StmtPrinter.cpp head/contrib/llvm/tools/clang/lib/Analysis/Consumed.cpp head/contrib/llvm/tools/clang/lib/Basic/Targets.cpp head/contrib/llvm/tools/clang/lib/Basic/Version.cpp head/contrib/llvm/tools/clang/lib/Driver/Driver.cpp head/contrib/llvm/tools/clang/lib/Driver/ToolChain.cpp head/contrib/llvm/tools/clang/lib/Driver/ToolChains.cpp head/contrib/llvm/tools/clang/lib/Driver/ToolChains.h head/contrib/llvm/tools/clang/lib/Driver/Tools.cpp head/contrib/llvm/tools/clang/lib/Sema/SemaExprCXX.cpp head/etc/mtree/BSD.include.dist head/lib/clang/include/Makefile head/lib/clang/include/clang/Basic/Version.inc head/lib/clang/include/llvm/Config/config.h head/lib/clang/include/llvm/Config/llvm-config.h head/tools/build/mk/OptionalObsoleteFiles.inc Directory Properties: head/contrib/llvm/ (props changed) head/contrib/llvm/tools/clang/ (props changed) Modified: head/ObsoleteFiles.inc ============================================================================== --- head/ObsoleteFiles.inc Mon May 12 17:58:17 2014 (r265924) +++ head/ObsoleteFiles.inc Mon May 12 18:45:56 2014 (r265925) @@ -38,6 +38,43 @@ # xargs -n1 | sort | uniq -d; # done +# 20140512: new clang import which bumps version from 3.4 to 3.4.1. +OLD_FILES+=usr/include/clang/3.4/__wmmintrin_aes.h +OLD_FILES+=usr/include/clang/3.4/__wmmintrin_pclmul.h +OLD_FILES+=usr/include/clang/3.4/altivec.h +OLD_FILES+=usr/include/clang/3.4/ammintrin.h +OLD_FILES+=usr/include/clang/3.4/avx2intrin.h +OLD_FILES+=usr/include/clang/3.4/avxintrin.h +OLD_FILES+=usr/include/clang/3.4/bmi2intrin.h +OLD_FILES+=usr/include/clang/3.4/bmiintrin.h +OLD_FILES+=usr/include/clang/3.4/cpuid.h +OLD_FILES+=usr/include/clang/3.4/emmintrin.h +OLD_FILES+=usr/include/clang/3.4/f16cintrin.h +OLD_FILES+=usr/include/clang/3.4/fma4intrin.h +OLD_FILES+=usr/include/clang/3.4/fmaintrin.h +OLD_FILES+=usr/include/clang/3.4/immintrin.h +OLD_FILES+=usr/include/clang/3.4/lzcntintrin.h +OLD_FILES+=usr/include/clang/3.4/mm3dnow.h +OLD_FILES+=usr/include/clang/3.4/mm_malloc.h +OLD_FILES+=usr/include/clang/3.4/mmintrin.h +OLD_FILES+=usr/include/clang/3.4/module.map +OLD_FILES+=usr/include/clang/3.4/nmmintrin.h +OLD_FILES+=usr/include/clang/3.4/pmmintrin.h +OLD_FILES+=usr/include/clang/3.4/popcntintrin.h +OLD_FILES+=usr/include/clang/3.4/prfchwintrin.h +OLD_FILES+=usr/include/clang/3.4/rdseedintrin.h +OLD_FILES+=usr/include/clang/3.4/rtmintrin.h +OLD_FILES+=usr/include/clang/3.4/shaintrin.h +OLD_FILES+=usr/include/clang/3.4/smmintrin.h +OLD_FILES+=usr/include/clang/3.4/tbmintrin.h +OLD_FILES+=usr/include/clang/3.4/tmmintrin.h +OLD_FILES+=usr/include/clang/3.4/wmmintrin.h +OLD_FILES+=usr/include/clang/3.4/x86intrin.h +OLD_FILES+=usr/include/clang/3.4/xmmintrin.h +OLD_FILES+=usr/include/clang/3.4/xopintrin.h +OLD_FILES+=usr/include/clang/3.4/arm_neon.h +OLD_FILES+=usr/include/clang/3.4/module.map +OLD_DIRS+=usr/include/clang/3.4 # 20140505: Bogusly installing src.opts.mk OLD_FILES+=usr/share/mk/src.opts.mk # 20140505: Reject PR kern/187551 Modified: head/UPDATING ============================================================================== --- head/UPDATING Mon May 12 17:58:17 2014 (r265924) +++ head/UPDATING Mon May 12 18:45:56 2014 (r265925) @@ -31,6 +31,9 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 11 disable the most expensive debugging functionality run "ln -s 'abort:false,junk:false' /etc/malloc.conf".) +20140512: + Clang and llvm have been upgraded to 3.4.1 release. + 20140508: We bogusly installed src.opts.mk in /usr/share/mk. This file should be removed to avoid issues in the future (and has been added to Modified: head/contrib/llvm/include/llvm/IR/IntrinsicsX86.td ============================================================================== --- head/contrib/llvm/include/llvm/IR/IntrinsicsX86.td Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/include/llvm/IR/IntrinsicsX86.td Mon May 12 18:45:56 2014 (r265925) @@ -1758,68 +1758,68 @@ let TargetPrefix = "x86" in { // All in def int_x86_avx2_gather_d_pd : GCCBuiltin<"__builtin_ia32_gatherd_pd">, Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v2f64_ty, llvm_i8_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx2_gather_d_pd_256 : GCCBuiltin<"__builtin_ia32_gatherd_pd256">, Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v4f64_ty, llvm_i8_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx2_gather_q_pd : GCCBuiltin<"__builtin_ia32_gatherq_pd">, Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_v2f64_ty, llvm_i8_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx2_gather_q_pd_256 : GCCBuiltin<"__builtin_ia32_gatherq_pd256">, Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_v4f64_ty, llvm_i8_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx2_gather_d_ps : GCCBuiltin<"__builtin_ia32_gatherd_ps">, Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v4f32_ty, llvm_i8_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx2_gather_d_ps_256 : GCCBuiltin<"__builtin_ia32_gatherd_ps256">, Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_ptr_ty, llvm_v8i32_ty, llvm_v8f32_ty, llvm_i8_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx2_gather_q_ps : GCCBuiltin<"__builtin_ia32_gatherq_ps">, Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_v4f32_ty, llvm_i8_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx2_gather_q_ps_256 : GCCBuiltin<"__builtin_ia32_gatherq_ps256">, Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_v4f32_ty, llvm_i8_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx2_gather_d_q : GCCBuiltin<"__builtin_ia32_gatherd_q">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v2i64_ty, llvm_i8_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx2_gather_d_q_256 : GCCBuiltin<"__builtin_ia32_gatherd_q256">, Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v4i64_ty, llvm_i8_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx2_gather_q_q : GCCBuiltin<"__builtin_ia32_gatherq_q">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_v2i64_ty, llvm_i8_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx2_gather_q_q_256 : GCCBuiltin<"__builtin_ia32_gatherq_q256">, Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_v4i64_ty, llvm_i8_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx2_gather_d_d : GCCBuiltin<"__builtin_ia32_gatherd_d">, Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_ptr_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx2_gather_d_d_256 : GCCBuiltin<"__builtin_ia32_gatherd_d256">, Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_ptr_ty, llvm_v8i32_ty, llvm_v8i32_ty, llvm_i8_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx2_gather_q_d : GCCBuiltin<"__builtin_ia32_gatherq_d">, Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_ptr_ty, llvm_v2i64_ty, llvm_v4i32_ty, llvm_i8_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx2_gather_q_d_256 : GCCBuiltin<"__builtin_ia32_gatherq_d256">, Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_ptr_ty, llvm_v4i64_ty, llvm_v4i32_ty, llvm_i8_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; } // Misc. @@ -2909,28 +2909,28 @@ let TargetPrefix = "x86" in { def int_x86_avx512_gather_dpd_mask_512 : GCCBuiltin<"__builtin_ia32_mask_gatherdpd512">, Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty, llvm_i8_ty, llvm_v8i32_ty, llvm_ptr_ty, llvm_i32_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx512_gather_dps_mask_512 : GCCBuiltin<"__builtin_ia32_mask_gatherdps512">, Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty, llvm_i16_ty, llvm_v16i32_ty, llvm_ptr_ty, llvm_i32_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx512_gather_qpd_mask_512 : GCCBuiltin<"__builtin_ia32_mask_gatherqpd512">, Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty, llvm_i8_ty, llvm_v8i64_ty, llvm_ptr_ty, llvm_i32_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx512_gather_qps_mask_512 : GCCBuiltin<"__builtin_ia32_mask_gatherqps512">, Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_i8_ty, llvm_v8i64_ty, llvm_ptr_ty, llvm_i32_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx512_gather_dpd_512 : GCCBuiltin<"__builtin_ia32_gatherdpd512">, Intrinsic<[llvm_v8f64_ty], [llvm_v8i32_ty, llvm_ptr_ty, llvm_i32_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx512_gather_dps_512 : GCCBuiltin<"__builtin_ia32_gatherdps512">, Intrinsic<[llvm_v16f32_ty], [llvm_v16i32_ty, llvm_ptr_ty, llvm_i32_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx512_gather_qpd_512 : GCCBuiltin<"__builtin_ia32_gatherqpd512">, Intrinsic<[llvm_v8f64_ty], [llvm_v8i64_ty, llvm_ptr_ty, llvm_i32_ty], @@ -2938,12 +2938,12 @@ let TargetPrefix = "x86" in { def int_x86_avx512_gather_qps_512 : GCCBuiltin<"__builtin_ia32_gatherqps512">, Intrinsic<[llvm_v8f32_ty], [llvm_v8i64_ty, llvm_ptr_ty, llvm_i32_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx512_gather_dpq_mask_512 : GCCBuiltin<"__builtin_ia32_mask_gatherdpq512">, Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_i8_ty, llvm_v8i32_ty, llvm_ptr_ty, llvm_i32_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx512_gather_dpi_mask_512 : GCCBuiltin<"__builtin_ia32_mask_gatherdpi512">, Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_i16_ty, llvm_v16i32_ty, llvm_ptr_ty, llvm_i32_ty], @@ -2955,7 +2955,7 @@ let TargetPrefix = "x86" in { def int_x86_avx512_gather_qpi_mask_512 : GCCBuiltin<"__builtin_ia32_mask_gatherqpi512">, Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_i8_ty, llvm_v8i64_ty, llvm_ptr_ty, llvm_i32_ty], - [IntrReadMem]>; + [IntrReadArgMem]>; def int_x86_avx512_gather_dpq_512 : GCCBuiltin<"__builtin_ia32_gatherdpq512">, Intrinsic<[llvm_v8i64_ty], [llvm_v8i32_ty, llvm_ptr_ty, Modified: head/contrib/llvm/include/llvm/MC/MCAsmInfo.h ============================================================================== --- head/contrib/llvm/include/llvm/MC/MCAsmInfo.h Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/include/llvm/MC/MCAsmInfo.h Mon May 12 18:45:56 2014 (r265925) @@ -266,13 +266,16 @@ namespace llvm { /// global as being a weak undefined symbol. const char *WeakRefDirective; // Defaults to NULL. - /// WeakDefDirective - This directive, if non-null, is used to declare a - /// global as being a weak defined symbol. - const char *WeakDefDirective; // Defaults to NULL. - - /// LinkOnceDirective - This directive, if non-null is used to declare a - /// global as being a weak defined symbol. This is used on cygwin/mingw. - const char *LinkOnceDirective; // Defaults to NULL. + /// True if we have a directive to declare a global as being a weak + /// defined symbol. + bool HasWeakDefDirective; // Defaults to false. + + /// True if we have a directive to declare a global as being a weak + /// defined symbol that can be hidden (unexported). + bool HasWeakDefCanBeHiddenDirective; // Defaults to false. + + /// True if we have a .linkonce directive. This is used on cygwin/mingw. + bool HasLinkOnceDirective; // Defaults to false. /// HiddenVisibilityAttr - This attribute, if not MCSA_Invalid, is used to /// declare a symbol as having hidden visibility. @@ -303,6 +306,10 @@ namespace llvm { /// uses relocations for references to other .debug_* sections. bool DwarfUsesRelocationsAcrossSections; + /// DwarfFDESymbolsUseAbsDiff - true if DWARF FDE symbol reference + /// relocations should be replaced by an absolute difference. + bool DwarfFDESymbolsUseAbsDiff; + /// DwarfRegNumForCFI - True if dwarf register numbers are printed /// instead of symbolic register names in .cfi_* directives. bool DwarfRegNumForCFI; // Defaults to false; @@ -497,8 +504,11 @@ namespace llvm { bool hasIdentDirective() const { return HasIdentDirective; } bool hasNoDeadStrip() const { return HasNoDeadStrip; } const char *getWeakRefDirective() const { return WeakRefDirective; } - const char *getWeakDefDirective() const { return WeakDefDirective; } - const char *getLinkOnceDirective() const { return LinkOnceDirective; } + bool hasWeakDefDirective() const { return HasWeakDefDirective; } + bool hasWeakDefCanBeHiddenDirective() const { + return HasWeakDefCanBeHiddenDirective; + } + bool hasLinkOnceDirective() const { return HasLinkOnceDirective; } MCSymbolAttr getHiddenVisibilityAttr() const { return HiddenVisibilityAttr;} MCSymbolAttr getHiddenDeclarationVisibilityAttr() const { @@ -528,6 +538,9 @@ namespace llvm { bool doesDwarfUseRelocationsAcrossSections() const { return DwarfUsesRelocationsAcrossSections; } + bool doDwarfFDESymbolsUseAbsDiff() const { + return DwarfFDESymbolsUseAbsDiff; + } bool useDwarfRegNumForCFI() const { return DwarfRegNumForCFI; } Modified: head/contrib/llvm/lib/Analysis/BasicAliasAnalysis.cpp ============================================================================== --- head/contrib/llvm/lib/Analysis/BasicAliasAnalysis.cpp Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/Analysis/BasicAliasAnalysis.cpp Mon May 12 18:45:56 2014 (r265925) @@ -18,7 +18,10 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Analysis/CaptureTracking.h" +#include "llvm/Analysis/CFG.h" +#include "llvm/Analysis/Dominators.h" #include "llvm/Analysis/InstructionSimplify.h" +#include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/MemoryBuiltins.h" #include "llvm/Analysis/ValueTracking.h" #include "llvm/IR/Constants.h" @@ -38,6 +41,12 @@ #include <algorithm> using namespace llvm; +/// Cutoff after which to stop analysing a set of phi nodes potentially involved +/// in a cycle. Because we are analysing 'through' phi nodes we need to be +/// careful with value equivalence. We use reachability to make sure a value +/// cannot be involved in a cycle. +const unsigned MaxNumPhiBBsValueReachabilityCheck = 20; + //===----------------------------------------------------------------------===// // Useful predicates //===----------------------------------------------------------------------===// @@ -403,42 +412,6 @@ DecomposeGEPExpression(const Value *V, i return V; } -/// GetIndexDifference - Dest and Src are the variable indices from two -/// decomposed GetElementPtr instructions GEP1 and GEP2 which have common base -/// pointers. Subtract the GEP2 indices from GEP1 to find the symbolic -/// difference between the two pointers. -static void GetIndexDifference(SmallVectorImpl<VariableGEPIndex> &Dest, - const SmallVectorImpl<VariableGEPIndex> &Src) { - if (Src.empty()) return; - - for (unsigned i = 0, e = Src.size(); i != e; ++i) { - const Value *V = Src[i].V; - ExtensionKind Extension = Src[i].Extension; - int64_t Scale = Src[i].Scale; - - // Find V in Dest. This is N^2, but pointer indices almost never have more - // than a few variable indexes. - for (unsigned j = 0, e = Dest.size(); j != e; ++j) { - if (Dest[j].V != V || Dest[j].Extension != Extension) continue; - - // If we found it, subtract off Scale V's from the entry in Dest. If it - // goes to zero, remove the entry. - if (Dest[j].Scale != Scale) - Dest[j].Scale -= Scale; - else - Dest.erase(Dest.begin()+j); - Scale = 0; - break; - } - - // If we didn't consume this entry, add it to the end of the Dest list. - if (Scale) { - VariableGEPIndex Entry = { V, Extension, -Scale }; - Dest.push_back(Entry); - } - } -} - //===----------------------------------------------------------------------===// // BasicAliasAnalysis Pass //===----------------------------------------------------------------------===// @@ -492,6 +465,7 @@ namespace { // SmallDenseMap if it ever grows larger. // FIXME: This should really be shrink_to_inline_capacity_and_clear(). AliasCache.shrink_and_clear(); + VisitedPhiBBs.clear(); return Alias; } @@ -532,9 +506,39 @@ namespace { typedef SmallDenseMap<LocPair, AliasResult, 8> AliasCacheTy; AliasCacheTy AliasCache; + /// \brief Track phi nodes we have visited. When interpret "Value" pointer + /// equality as value equality we need to make sure that the "Value" is not + /// part of a cycle. Otherwise, two uses could come from different + /// "iterations" of a cycle and see different values for the same "Value" + /// pointer. + /// The following example shows the problem: + /// %p = phi(%alloca1, %addr2) + /// %l = load %ptr + /// %addr1 = gep, %alloca2, 0, %l + /// %addr2 = gep %alloca2, 0, (%l + 1) + /// alias(%p, %addr1) -> MayAlias ! + /// store %l, ... + SmallPtrSet<const BasicBlock*, 8> VisitedPhiBBs; + // Visited - Track instructions visited by pointsToConstantMemory. SmallPtrSet<const Value*, 16> Visited; + /// \brief Check whether two Values can be considered equivalent. + /// + /// In addition to pointer equivalence of \p V1 and \p V2 this checks + /// whether they can not be part of a cycle in the value graph by looking at + /// all visited phi nodes an making sure that the phis cannot reach the + /// value. We have to do this because we are looking through phi nodes (That + /// is we say noalias(V, phi(VA, VB)) if noalias(V, VA) and noalias(V, VB). + bool isValueEqualInPotentialCycles(const Value *V1, const Value *V2); + + /// \brief Dest and Src are the variable indices from two decomposed + /// GetElementPtr instructions GEP1 and GEP2 which have common base + /// pointers. Subtract the GEP2 indices from GEP1 to find the symbolic + /// difference between the two pointers. + void GetIndexDifference(SmallVectorImpl<VariableGEPIndex> &Dest, + const SmallVectorImpl<VariableGEPIndex> &Src); + // aliasGEP - Provide a bunch of ad-hoc rules to disambiguate a GEP // instruction against another. AliasResult aliasGEP(const GEPOperator *V1, uint64_t V1Size, @@ -1005,7 +1009,15 @@ BasicAliasAnalysis::aliasGEP(const GEPOp return NoAlias; } } else { - if (V1Size != UnknownSize) { + // We have the situation where: + // + + + // | BaseOffset | + // ---------------->| + // |-->V1Size |-------> V2Size + // GEP1 V2 + // We need to know that V2Size is not unknown, otherwise we might have + // stripped a gep with negative index ('gep <ptr>, -1, ...). + if (V1Size != UnknownSize && V2Size != UnknownSize) { if (-(uint64_t)GEP1BaseOffset < V1Size) return PartialAlias; return NoAlias; @@ -1094,6 +1106,10 @@ BasicAliasAnalysis::aliasPHI(const PHINo const MDNode *PNTBAAInfo, const Value *V2, uint64_t V2Size, const MDNode *V2TBAAInfo) { + // Track phi nodes we have visited. We use this information when we determine + // value equivalence. + VisitedPhiBBs.insert(PN->getParent()); + // If the values are PHIs in the same block, we can do a more precise // as well as efficient check: just check for aliases between the values // on corresponding edges. @@ -1187,7 +1203,13 @@ BasicAliasAnalysis::aliasCheck(const Val V2 = V2->stripPointerCasts(); // Are we checking for alias of the same value? - if (V1 == V2) return MustAlias; + // Because we look 'through' phi nodes we could look at "Value" pointers from + // different iterations. We must therefore make sure that this is not the + // case. The function isValueEqualInPotentialCycles ensures that this cannot + // happen by looking at the visited phi nodes and making sure they cannot + // reach the value. + if (isValueEqualInPotentialCycles(V1, V2)) + return MustAlias; if (!V1->getType()->isPointerTy() || !V2->getType()->isPointerTy()) return NoAlias; // Scalars cannot alias each other @@ -1307,3 +1329,71 @@ BasicAliasAnalysis::aliasCheck(const Val Location(V2, V2Size, V2TBAAInfo)); return AliasCache[Locs] = Result; } + +bool BasicAliasAnalysis::isValueEqualInPotentialCycles(const Value *V, + const Value *V2) { + if (V != V2) + return false; + + const Instruction *Inst = dyn_cast<Instruction>(V); + if (!Inst) + return true; + + if (VisitedPhiBBs.size() > MaxNumPhiBBsValueReachabilityCheck) + return false; + + // Use dominance or loop info if available. + DominatorTree *DT = getAnalysisIfAvailable<DominatorTree>(); + LoopInfo *LI = getAnalysisIfAvailable<LoopInfo>(); + + // Make sure that the visited phis cannot reach the Value. This ensures that + // the Values cannot come from different iterations of a potential cycle the + // phi nodes could be involved in. + for (SmallPtrSet<const BasicBlock *, 8>::iterator PI = VisitedPhiBBs.begin(), + PE = VisitedPhiBBs.end(); + PI != PE; ++PI) + if (isPotentiallyReachable((*PI)->begin(), Inst, DT, LI)) + return false; + + return true; +} + +/// GetIndexDifference - Dest and Src are the variable indices from two +/// decomposed GetElementPtr instructions GEP1 and GEP2 which have common base +/// pointers. Subtract the GEP2 indices from GEP1 to find the symbolic +/// difference between the two pointers. +void BasicAliasAnalysis::GetIndexDifference( + SmallVectorImpl<VariableGEPIndex> &Dest, + const SmallVectorImpl<VariableGEPIndex> &Src) { + if (Src.empty()) + return; + + for (unsigned i = 0, e = Src.size(); i != e; ++i) { + const Value *V = Src[i].V; + ExtensionKind Extension = Src[i].Extension; + int64_t Scale = Src[i].Scale; + + // Find V in Dest. This is N^2, but pointer indices almost never have more + // than a few variable indexes. + for (unsigned j = 0, e = Dest.size(); j != e; ++j) { + if (!isValueEqualInPotentialCycles(Dest[j].V, V) || + Dest[j].Extension != Extension) + continue; + + // If we found it, subtract off Scale V's from the entry in Dest. If it + // goes to zero, remove the entry. + if (Dest[j].Scale != Scale) + Dest[j].Scale -= Scale; + else + Dest.erase(Dest.begin() + j); + Scale = 0; + break; + } + + // If we didn't consume this entry, add it to the end of the Dest list. + if (Scale) { + VariableGEPIndex Entry = { V, Extension, -Scale }; + Dest.push_back(Entry); + } + } +} Modified: head/contrib/llvm/lib/Analysis/IVUsers.cpp ============================================================================== --- head/contrib/llvm/lib/Analysis/IVUsers.cpp Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/Analysis/IVUsers.cpp Mon May 12 18:45:56 2014 (r265925) @@ -187,15 +187,34 @@ bool IVUsers::AddUsersImpl(Instruction * if (AddUserToIVUsers) { // Okay, we found a user that we cannot reduce. - IVUses.push_back(new IVStrideUse(this, User, I)); - IVStrideUse &NewUse = IVUses.back(); + IVStrideUse &NewUse = AddUser(User, I); // Autodetect the post-inc loop set, populating NewUse.PostIncLoops. // The regular return value here is discarded; instead of recording // it, we just recompute it when we need it. + const SCEV *OriginalISE = ISE; ISE = TransformForPostIncUse(NormalizeAutodetect, ISE, User, I, NewUse.PostIncLoops, *SE, *DT); + + // PostIncNormalization effectively simplifies the expression under + // pre-increment assumptions. Those assumptions (no wrapping) might not + // hold for the post-inc value. Catch such cases by making sure the + // transformation is invertible. + if (OriginalISE != ISE) { + const SCEV *DenormalizedISE = + TransformForPostIncUse(Denormalize, ISE, User, I, + NewUse.PostIncLoops, *SE, *DT); + + // If we normalized the expression, but denormalization doesn't give the + // original one, discard this user. + if (OriginalISE != DenormalizedISE) { + DEBUG(dbgs() << " DISCARDING (NORMALIZATION ISN'T INVERTIBLE): " + << *ISE << '\n'); + IVUses.pop_back(); + return false; + } + } DEBUG(if (SE->getSCEV(I) != ISE) dbgs() << " NORMALIZED TO: " << *ISE << '\n'); } Modified: head/contrib/llvm/lib/Analysis/ScalarEvolution.cpp ============================================================================== --- head/contrib/llvm/lib/Analysis/ScalarEvolution.cpp Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/Analysis/ScalarEvolution.cpp Mon May 12 18:45:56 2014 (r265925) @@ -6218,7 +6218,7 @@ bool ScalarEvolution::isImpliedCond(ICmp // LHS' type is checked for above. if (getTypeSizeInBits(LHS->getType()) > getTypeSizeInBits(FoundLHS->getType())) { - if (CmpInst::isSigned(Pred)) { + if (CmpInst::isSigned(FoundPred)) { FoundLHS = getSignExtendExpr(FoundLHS, LHS->getType()); FoundRHS = getSignExtendExpr(FoundRHS, LHS->getType()); } else { Modified: head/contrib/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp ============================================================================== --- head/contrib/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Mon May 12 18:45:56 2014 (r265925) @@ -223,13 +223,14 @@ void AsmPrinter::EmitLinkage(const Globa case GlobalValue::WeakAnyLinkage: case GlobalValue::WeakODRLinkage: case GlobalValue::LinkerPrivateWeakLinkage: - if (MAI->getWeakDefDirective() != 0) { + if (MAI->hasWeakDefDirective()) { // .globl _foo OutStreamer.EmitSymbolAttribute(GVSym, MCSA_Global); bool CanBeHidden = false; - if (Linkage == GlobalValue::LinkOnceODRLinkage) { + if (Linkage == GlobalValue::LinkOnceODRLinkage && + MAI->hasWeakDefCanBeHiddenDirective()) { if (GV->hasUnnamedAddr()) { CanBeHidden = true; } else { @@ -244,7 +245,7 @@ void AsmPrinter::EmitLinkage(const Globa OutStreamer.EmitSymbolAttribute(GVSym, MCSA_WeakDefinition); else OutStreamer.EmitSymbolAttribute(GVSym, MCSA_WeakDefAutoPrivate); - } else if (MAI->getLinkOnceDirective() != 0) { + } else if (MAI->hasLinkOnceDirective()) { // .globl _foo OutStreamer.EmitSymbolAttribute(GVSym, MCSA_Global); //NOTE: linkonce is handled by the section the symbol was assigned to. Modified: head/contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp ============================================================================== --- head/contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon May 12 18:45:56 2014 (r265925) @@ -8547,7 +8547,10 @@ struct MemOpLink { // base ptr. struct ConsecutiveMemoryChainSorter { bool operator()(MemOpLink LHS, MemOpLink RHS) { - return LHS.OffsetFromBase < RHS.OffsetFromBase; + return + LHS.OffsetFromBase < RHS.OffsetFromBase || + (LHS.OffsetFromBase == RHS.OffsetFromBase && + LHS.SequenceNum > RHS.SequenceNum); } }; Modified: head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp ============================================================================== --- head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Mon May 12 18:45:56 2014 (r265925) @@ -210,6 +210,7 @@ SDValue VectorLegalizer::LegalizeOp(SDVa case ISD::SRL: case ISD::ROTL: case ISD::ROTR: + case ISD::BSWAP: case ISD::CTLZ: case ISD::CTTZ: case ISD::CTLZ_ZERO_UNDEF: Modified: head/contrib/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp ============================================================================== --- head/contrib/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Mon May 12 18:45:56 2014 (r265925) @@ -219,8 +219,11 @@ void ScheduleDAGSDNodes::ClusterNeighbor DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode. bool Cluster = false; SDNode *Base = Node; + // This algorithm requires a reasonably low use count before finding a match + // to avoid uselessly blowing up compile time in large blocks. + unsigned UseCount = 0; for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end(); - I != E; ++I) { + I != E && UseCount < 100; ++I, ++UseCount) { SDNode *User = *I; if (User == Node || !Visited.insert(User)) continue; @@ -237,6 +240,8 @@ void ScheduleDAGSDNodes::ClusterNeighbor if (Offset2 < Offset1) Base = User; Cluster = true; + // Reset UseCount to allow more matches. + UseCount = 0; } if (!Cluster) Modified: head/contrib/llvm/lib/MC/MCAsmInfo.cpp ============================================================================== --- head/contrib/llvm/lib/MC/MCAsmInfo.cpp Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/MC/MCAsmInfo.cpp Mon May 12 18:45:56 2014 (r265925) @@ -76,8 +76,9 @@ MCAsmInfo::MCAsmInfo() { HasIdentDirective = false; HasNoDeadStrip = false; WeakRefDirective = 0; - WeakDefDirective = 0; - LinkOnceDirective = 0; + HasWeakDefDirective = false; + HasWeakDefCanBeHiddenDirective = false; + HasLinkOnceDirective = false; HiddenVisibilityAttr = MCSA_Hidden; HiddenDeclarationVisibilityAttr = MCSA_Hidden; ProtectedVisibilityAttr = MCSA_Protected; @@ -85,6 +86,7 @@ MCAsmInfo::MCAsmInfo() { SupportsDebugInformation = false; ExceptionsType = ExceptionHandling::None; DwarfUsesRelocationsAcrossSections = true; + DwarfFDESymbolsUseAbsDiff = false; DwarfRegNumForCFI = false; HasMicrosoftFastStdCallMangling = false; NeedsDwarfSectionOffsetDirective = false; Modified: head/contrib/llvm/lib/MC/MCAsmInfoCOFF.cpp ============================================================================== --- head/contrib/llvm/lib/MC/MCAsmInfoCOFF.cpp Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/MC/MCAsmInfoCOFF.cpp Mon May 12 18:45:56 2014 (r265925) @@ -27,7 +27,7 @@ MCAsmInfoCOFF::MCAsmInfoCOFF() { HasSingleParameterDotFile = false; PrivateGlobalPrefix = "L"; // Prefix for private global symbols WeakRefDirective = "\t.weak\t"; - LinkOnceDirective = "\t.linkonce discard\n"; + HasLinkOnceDirective = true; // Doesn't support visibility: HiddenVisibilityAttr = HiddenDeclarationVisibilityAttr = MCSA_Invalid; Modified: head/contrib/llvm/lib/MC/MCAsmInfoDarwin.cpp ============================================================================== --- head/contrib/llvm/lib/MC/MCAsmInfoDarwin.cpp Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/MC/MCAsmInfoDarwin.cpp Mon May 12 18:45:56 2014 (r265925) @@ -36,7 +36,8 @@ MCAsmInfoDarwin::MCAsmInfoDarwin() { InlineAsmEnd = " InlineAsm End"; // Directives: - WeakDefDirective = "\t.weak_definition "; + HasWeakDefDirective = true; + HasWeakDefCanBeHiddenDirective = true; WeakRefDirective = "\t.weak_reference "; ZeroDirective = "\t.space\t"; // ".space N" emits N zeros. HasMachoZeroFillDirective = true; // Uses .zerofill Modified: head/contrib/llvm/lib/MC/MCDwarf.cpp ============================================================================== --- head/contrib/llvm/lib/MC/MCDwarf.cpp Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/MC/MCDwarf.cpp Mon May 12 18:45:56 2014 (r265925) @@ -839,8 +839,9 @@ static unsigned getSizeForEncoding(MCStr } } -static void EmitSymbol(MCStreamer &streamer, const MCSymbol &symbol, - unsigned symbolEncoding, const char *comment = 0) { +static void EmitFDESymbol(MCStreamer &streamer, const MCSymbol &symbol, + unsigned symbolEncoding, bool isEH, + const char *comment = 0) { MCContext &context = streamer.getContext(); const MCAsmInfo *asmInfo = context.getAsmInfo(); const MCExpr *v = asmInfo->getExprForFDESymbol(&symbol, @@ -848,7 +849,10 @@ static void EmitSymbol(MCStreamer &strea streamer); unsigned size = getSizeForEncoding(streamer, symbolEncoding); if (streamer.isVerboseAsm() && comment) streamer.AddComment(comment); - streamer.EmitAbsValue(v, size); + if (asmInfo->doDwarfFDESymbolsUseAbsDiff() && isEH) + streamer.EmitAbsValue(v, size); + else + streamer.EmitValue(v, size); } static void EmitPersonality(MCStreamer &streamer, const MCSymbol &symbol, @@ -1347,7 +1351,7 @@ MCSymbol *FrameEmitterImpl::EmitFDE(MCSt unsigned PCEncoding = IsEH ? MOFI->getFDEEncoding(UsingCFI) : (unsigned)dwarf::DW_EH_PE_absptr; unsigned PCSize = getSizeForEncoding(streamer, PCEncoding); - EmitSymbol(streamer, *frame.Begin, PCEncoding, "FDE initial location"); + EmitFDESymbol(streamer, *frame.Begin, PCEncoding, IsEH, "FDE initial location"); // PC Range const MCExpr *Range = MakeStartMinusEndExpr(streamer, *frame.Begin, @@ -1367,8 +1371,8 @@ MCSymbol *FrameEmitterImpl::EmitFDE(MCSt // Augmentation Data if (frame.Lsda) - EmitSymbol(streamer, *frame.Lsda, frame.LsdaEncoding, - "Language Specific Data Area"); + EmitFDESymbol(streamer, *frame.Lsda, frame.LsdaEncoding, true, + "Language Specific Data Area"); } // Call Frame Instructions Modified: head/contrib/llvm/lib/MC/MCParser/AsmParser.cpp ============================================================================== --- head/contrib/llvm/lib/MC/MCParser/AsmParser.cpp Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/MC/MCParser/AsmParser.cpp Mon May 12 18:45:56 2014 (r265925) @@ -4297,6 +4297,10 @@ bool AsmParser::parseMSInlineAsm( break; } case AOK_DotOperator: + // Insert the dot if the user omitted it. + OS.flush(); + if (AsmStringIR.at(AsmStringIR.size() - 1) != '.') + OS << '.'; OS << (*I).Val; break; } Modified: head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp ============================================================================== --- head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Mon May 12 18:45:56 2014 (r265925) @@ -31,12 +31,8 @@ using namespace llvm; static TargetLoweringObjectFile *createTLOF(AArch64TargetMachine &TM) { const AArch64Subtarget *Subtarget = &TM.getSubtarget<AArch64Subtarget>(); - - if (Subtarget->isTargetLinux()) - return new AArch64LinuxTargetObjectFile(); - if (Subtarget->isTargetELF()) - return new TargetLoweringObjectFileELF(); - llvm_unreachable("unknown subtarget type"); + assert (Subtarget->isTargetELF() && "unknown subtarget type"); + return new AArch64ElfTargetObjectFile(); } AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM) @@ -2782,7 +2778,7 @@ AArch64TargetLowering::LowerSETCC(SDValu SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); - const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); + const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); // We have to make sure we copy the entire structure: 8+8+8+4+4 = 32 bytes // rather than just 8. Modified: head/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.td ============================================================================== --- head/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.td Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.td Mon May 12 18:45:56 2014 (r265925) @@ -2587,6 +2587,7 @@ class A64I_SRexs_impl<bits<2> size, bits pat, itin> { let mayStore = 1; let PostEncoderMethod = "fixLoadStoreExclusive<1,0>"; + let Constraints = "@earlyclobber $Rs"; } multiclass A64I_SRex<string asmstr, bits<3> opcode, string prefix> { Modified: head/contrib/llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp ============================================================================== --- head/contrib/llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp Mon May 12 18:45:56 2014 (r265925) @@ -22,3 +22,10 @@ AArch64LinuxTargetObjectFile::Initialize TargetLoweringObjectFileELF::Initialize(Ctx, TM); InitializeELF(TM.Options.UseInitArray); } + +void +AArch64ElfTargetObjectFile::Initialize(MCContext &Ctx, + const TargetMachine &TM) { + TargetLoweringObjectFileELF::Initialize(Ctx, TM); + InitializeELF(TM.Options.UseInitArray); +} Modified: head/contrib/llvm/lib/Target/AArch64/AArch64TargetObjectFile.h ============================================================================== --- head/contrib/llvm/lib/Target/AArch64/AArch64TargetObjectFile.h Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/Target/AArch64/AArch64TargetObjectFile.h Mon May 12 18:45:56 2014 (r265925) @@ -20,8 +20,12 @@ namespace llvm { - /// AArch64LinuxTargetObjectFile - This implementation is used for linux - /// AArch64. + /// AArch64ElfTargetObjectFile - This implementation is used for ELF + /// AArch64 targets. + class AArch64ElfTargetObjectFile : public TargetLoweringObjectFileELF { + virtual void Initialize(MCContext &Ctx, const TargetMachine &TM); + }; + class AArch64LinuxTargetObjectFile : public TargetLoweringObjectFileELF { virtual void Initialize(MCContext &Ctx, const TargetMachine &TM); }; Modified: head/contrib/llvm/lib/Target/ARM/A15SDOptimizer.cpp ============================================================================== --- head/contrib/llvm/lib/Target/ARM/A15SDOptimizer.cpp Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/Target/ARM/A15SDOptimizer.cpp Mon May 12 18:45:56 2014 (r265925) @@ -418,7 +418,8 @@ SmallVector<unsigned, 8> A15SDOptimizer: if (!MO.isReg() || !MO.isUse()) continue; if (!usesRegClass(MO, &ARM::DPRRegClass) && - !usesRegClass(MO, &ARM::QPRRegClass)) + !usesRegClass(MO, &ARM::QPRRegClass) && + !usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR continue; Defs.push_back(MO.getReg()); @@ -538,7 +539,10 @@ A15SDOptimizer::optimizeAllLanesPattern( InsertPt++; unsigned Out; - if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass)) { + // DPair has the same length as QPR and also has two DPRs as subreg. + // Treat DPair as QPR. + if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || + MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg, ARM::dsub_0, &ARM::DPRRegClass); unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg, @@ -571,7 +575,9 @@ A15SDOptimizer::optimizeAllLanesPattern( default: llvm_unreachable("Unknown preferred lane!"); } - bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass); + // Treat DPair as QPR + bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) || + usesRegClass(MI->getOperand(0), &ARM::DPairRegClass); Out = createImplicitDef(MBB, InsertPt, DL); Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg); Modified: head/contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp ============================================================================== --- head/contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp Mon May 12 18:45:56 2014 (r265925) @@ -3684,6 +3684,7 @@ ARMBaseInstrInfo::getOperandLatency(cons case ARM::VLD3d16Pseudo: case ARM::VLD3d32Pseudo: case ARM::VLD1d64TPseudo: + case ARM::VLD1d64TPseudoWB_fixed: case ARM::VLD3d8Pseudo_UPD: case ARM::VLD3d16Pseudo_UPD: case ARM::VLD3d32Pseudo_UPD: @@ -3700,6 +3701,7 @@ ARMBaseInstrInfo::getOperandLatency(cons case ARM::VLD4d16Pseudo: case ARM::VLD4d32Pseudo: case ARM::VLD1d64QPseudo: + case ARM::VLD1d64QPseudoWB_fixed: case ARM::VLD4d8Pseudo_UPD: case ARM::VLD4d16Pseudo_UPD: case ARM::VLD4d32Pseudo_UPD: Modified: head/contrib/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp ============================================================================== --- head/contrib/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp Mon May 12 18:45:56 2014 (r265925) @@ -136,7 +136,9 @@ static const NEONLdStTableEntry NEONLdSt { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true}, { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false}, +{ ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false}, { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false}, +{ ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false}, { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true}, { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true}, @@ -1071,6 +1073,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBa case ARM::VLD3d16Pseudo: case ARM::VLD3d32Pseudo: case ARM::VLD1d64TPseudo: + case ARM::VLD1d64TPseudoWB_fixed: case ARM::VLD3d8Pseudo_UPD: case ARM::VLD3d16Pseudo_UPD: case ARM::VLD3d32Pseudo_UPD: @@ -1087,6 +1090,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBa case ARM::VLD4d16Pseudo: case ARM::VLD4d32Pseudo: case ARM::VLD1d64QPseudo: + case ARM::VLD1d64QPseudoWB_fixed: case ARM::VLD4d8Pseudo_UPD: case ARM::VLD4d16Pseudo_UPD: case ARM::VLD4d32Pseudo_UPD: Modified: head/contrib/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ============================================================================== --- head/contrib/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon May 12 17:58:17 2014 (r265924) +++ head/contrib/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon May 12 18:45:56 2014 (r265925) @@ -1673,9 +1673,61 @@ SDValue ARMDAGToDAGISel::GetVLDSTAlign(S return CurDAG->getTargetConstant(Alignment, MVT::i32); } +static bool isVLDfixed(unsigned Opc) +{ + switch (Opc) { + default: return false; + case ARM::VLD1d8wb_fixed : return true; + case ARM::VLD1d16wb_fixed : return true; + case ARM::VLD1d64Qwb_fixed : return true; + case ARM::VLD1d32wb_fixed : return true; + case ARM::VLD1d64wb_fixed : return true; + case ARM::VLD1d64TPseudoWB_fixed : return true; + case ARM::VLD1d64QPseudoWB_fixed : return true; + case ARM::VLD1q8wb_fixed : return true; + case ARM::VLD1q16wb_fixed : return true; + case ARM::VLD1q32wb_fixed : return true; + case ARM::VLD1q64wb_fixed : return true; + case ARM::VLD2d8wb_fixed : return true; + case ARM::VLD2d16wb_fixed : return true; + case ARM::VLD2d32wb_fixed : return true; + case ARM::VLD2q8PseudoWB_fixed : return true; + case ARM::VLD2q16PseudoWB_fixed : return true; + case ARM::VLD2q32PseudoWB_fixed : return true; + case ARM::VLD2DUPd8wb_fixed : return true; + case ARM::VLD2DUPd16wb_fixed : return true; + case ARM::VLD2DUPd32wb_fixed : return true; + } +} + +static bool isVSTfixed(unsigned Opc) +{ + switch (Opc) { + default: return false; + case ARM::VST1d8wb_fixed : return true; + case ARM::VST1d16wb_fixed : return true; + case ARM::VST1d32wb_fixed : return true; + case ARM::VST1d64wb_fixed : return true; + case ARM::VST1q8wb_fixed : return true; + case ARM::VST1q16wb_fixed : return true; + case ARM::VST1q32wb_fixed : return true; + case ARM::VST1q64wb_fixed : return true; + case ARM::VST1d64TPseudoWB_fixed : return true; + case ARM::VST1d64QPseudoWB_fixed : return true; + case ARM::VST2d8wb_fixed : return true; + case ARM::VST2d16wb_fixed : return true; + case ARM::VST2d32wb_fixed : return true; + case ARM::VST2q8PseudoWB_fixed : return true; + case ARM::VST2q16PseudoWB_fixed : return true; + case ARM::VST2q32PseudoWB_fixed : return true; + } +} + // Get the register stride update opcode of a VLD/VST instruction that // is otherwise equivalent to the given fixed stride updating instruction. static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) { + assert((isVLDfixed(Opc) || isVSTfixed(Opc)) + && "Incorrect fixed stride updating instruction."); switch (Opc) { default: break; case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register; @@ -1686,6 +1738,10 @@ static unsigned getVLDSTRegisterUpdateOp case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register; case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register; case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register; + case ARM::VLD1d64Twb_fixed: return ARM::VLD1d64Twb_register; + case ARM::VLD1d64Qwb_fixed: return ARM::VLD1d64Qwb_register; + case ARM::VLD1d64TPseudoWB_fixed: return ARM::VLD1d64TPseudoWB_register; + case ARM::VLD1d64QPseudoWB_fixed: return ARM::VLD1d64QPseudoWB_register; case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register; case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register; @@ -1785,11 +1841,11 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNod SDValue Inc = N->getOperand(AddrOpIdx + 1); // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0 // case entirely when the rest are updated to that form, too. - if ((NumVecs == 1 || NumVecs == 2) && !isa<ConstantSDNode>(Inc.getNode())) + if ((NumVecs <= 2) && !isa<ConstantSDNode>(Inc.getNode())) Opc = getVLDSTRegisterUpdateOpcode(Opc); - // We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so + // FIXME: We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so // check for that explicitly too. Horribly hacky, but temporary. - if ((NumVecs != 1 && NumVecs != 2 && Opc != ARM::VLD1q64wb_fixed) || + if ((NumVecs > 2 && !isVLDfixed(Opc)) || !isa<ConstantSDNode>(Inc.getNode())) Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc); } @@ -1937,11 +1993,12 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNod // case entirely when the rest are updated to that form, too. if (NumVecs <= 2 && !isa<ConstantSDNode>(Inc.getNode())) Opc = getVLDSTRegisterUpdateOpcode(Opc); - // We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so + // FIXME: We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so // check for that explicitly too. Horribly hacky, but temporary. - if ((NumVecs > 2 && Opc != ARM::VST1q64wb_fixed) || - !isa<ConstantSDNode>(Inc.getNode())) - Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc); + if (!isa<ConstantSDNode>(Inc.getNode())) + Ops.push_back(Inc); + else if (NumVecs > 2 && !isVSTfixed(Opc)) + Ops.push_back(Reg0); } Ops.push_back(SrcReg); Ops.push_back(Pred); @@ -2834,7 +2891,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode * static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d16Pseudo_UPD, ARM::VLD3d32Pseudo_UPD, - ARM::VLD1q64wb_fixed}; + ARM::VLD1d64TPseudoWB_fixed}; static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q16Pseudo_UPD, ARM::VLD3q32Pseudo_UPD }; @@ -2848,7 +2905,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode * static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD, ARM::VLD4d32Pseudo_UPD, - ARM::VLD1q64wb_fixed}; + ARM::VLD1d64QPseudoWB_fixed}; static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q16Pseudo_UPD, ARM::VLD4q32Pseudo_UPD }; Modified: head/contrib/llvm/lib/Target/ARM/ARMInstrNEON.td ============================================================================== --- head/contrib/llvm/lib/Target/ARM/ARMInstrNEON.td Mon May 12 17:58:17 2014 (r265924) *** DIFF OUTPUT TRUNCATED AT 1000 LINES *** _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscr...@freebsd.org"