On Thu, Nov 27, 2014 at 11:28:31AM -0800, Adrian Chadd wrote: > On 27 November 2014 at 10:36, Ruslan Bukin <b...@freebsd.org> wrote: > > Hi, > > > > There is a theory that a problem is related to CPU caches, and it can be > > BERI-cpu > > specific only. > > > > And sorry I didn't realized virtio was still in the kernel when I was trying > > MDROOT (we do dcache operations in virtio). > > > > The workaround I found is to disable all the instruction cache invalidation > > calls > > (there are a few calls on cpu startup only). > > > > Hm, can we test this on real MIPS hardware, just to be sure? > > I can spin this up on MIPS24k/MIPS74k hardware early next week. >
It can be helpfull. It is easy to test, just insert mips_dcache_wbinv_all() call in some driver and ensure mips_cache_ops.mco_sdcache_wbinv_all is not NULL on your hardware, so the dcache invalidation call will invalidate both primary and secondary data caches. With virtio we are calling mips_dcache_wbinv_all() a few times per second (the good idea here is supposed to be more selective with physical addresses invalidation, but it should not hurt to data consistent as it do both writeback and flush) Ruslan _______________________________________________ svn-src-all@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscr...@freebsd.org"
