Author: ian
Date: Wed Dec 31 02:38:23 2014
New Revision: 276445
URL: https://svnweb.freebsd.org/changeset/base/276445
Log:
Change the order of operations for the initial cache setup. Turning off
the cache before clean/invalidate ensured that no new lines can come into
the cache or migrate between levels during the operation, but may not be
safe on some chips. Instead, if the cache was enabled on entry, do the
wbinv while it's still enabled, and then disable it and do a separate
invalidate pass. After the intitial writeback we know there are no
dirty lines left and no new dirty lines can be created as long as we
carefully avoid touching memory before turning the cache off. Add a
comment about that so no new code gets inserted between those points.
Modified:
head/sys/arm/arm/locore-v6.S
Modified: head/sys/arm/arm/locore-v6.S
==============================================================================
--- head/sys/arm/arm/locore-v6.S Wed Dec 31 02:33:12 2014
(r276444)
+++ head/sys/arm/arm/locore-v6.S Wed Dec 31 02:38:23 2014
(r276445)
@@ -84,11 +84,9 @@ ASENTRY_NP(_start)
*/
mrc CP15_SCTLR(r7)
tst r7, #CPU_CONTROL_DC_ENABLE
- beq 1f
- bic r7, #CPU_CONTROL_DC_ENABLE
- mcr CP15_SCTLR(r7)
- ISB
- bl dcache_wbinv_poc_all
+ blne dcache_wbinv_poc_all
+
+ /* ! Do not write to memory between wbinv and disabling cache ! */
/*
* Now there are no dirty lines, but there may still be lines marked
@@ -96,6 +94,7 @@ ASENTRY_NP(_start)
* before setting up new page tables and re-enabling the mmu.
*/
1:
+ bic r7, #CPU_CONTROL_DC_ENABLE
bic r7, #CPU_CONTROL_MMU_ENABLE
bic r7, #CPU_CONTROL_IC_ENABLE
bic r7, #CPU_CONTROL_UNAL_ENABLE
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