Author: rnoland
Date: Sat Mar 13 11:51:18 2010
New Revision: 205120
URL: http://svn.freebsd.org/changeset/base/205120
Log:
Add support for Intel Pineview chips, aka IGD
Slightly modified version of the submitted patch.
PR: 143427
Submitted by: Mamoru Sumida <msum...@mvc.biglobe.ne.jp>
MFC after: 3 days
Modified:
head/sys/dev/drm/drm_pciids.h
head/sys/dev/drm/i915_drv.h
head/sys/dev/drm/i915_reg.h
Modified: head/sys/dev/drm/drm_pciids.h
==============================================================================
--- head/sys/dev/drm/drm_pciids.h Sat Mar 13 11:17:39 2010
(r205119)
+++ head/sys/dev/drm/drm_pciids.h Sat Mar 13 11:51:18 2010
(r205120)
@@ -549,7 +549,9 @@
{0x8086, 0x29B2, CHIP_I9XX|CHIP_I915, "Intel Q35"}, \
{0x8086, 0x29D2, CHIP_I9XX|CHIP_I915, "Intel Q33"}, \
{0x8086, 0x2A42, CHIP_I9XX|CHIP_I965, "Mobile Intel® GM45 Express
Chipset"}, \
- {0x8086, 0x2E02, CHIP_I9XX|CHIP_I965, "Intel Integrated Graphics
Device"}, \
+ {0x8086, 0x2E02, CHIP_I9XX|CHIP_I965, "Intel Eaglelake"}, \
+ {0x8086, 0xA001, CHIP_I9XX|CHIP_I965, "Intel Pineview"}, \
+ {0x8086, 0xA011, CHIP_I9XX|CHIP_I965, "Intel Pineview (M)"}, \
{0x8086, 0x2E12, CHIP_I9XX|CHIP_I965, "Intel Q45/Q43"}, \
{0x8086, 0x2E22, CHIP_I9XX|CHIP_I965, "Intel G45/G43"}, \
{0x8086, 0x2E32, CHIP_I9XX|CHIP_I965, "Intel G41"}, \
Modified: head/sys/dev/drm/i915_drv.h
==============================================================================
--- head/sys/dev/drm/i915_drv.h Sat Mar 13 11:17:39 2010 (r205119)
+++ head/sys/dev/drm/i915_drv.h Sat Mar 13 11:51:18 2010 (r205120)
@@ -657,15 +657,21 @@ extern int i915_wait_ring(struct drm_dev
(dev)->pci_device == 0x2E32 || \
IS_GM45(dev))
+#define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
+#define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
+#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
+
#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
(dev)->pci_device == 0x29B2 || \
- (dev)->pci_device == 0x29D2)
+ (dev)->pci_device == 0x29D2 || \
+ IS_IGD(DEV))
#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
- IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
+ IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
+ IS_IGD(dev))
#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
Modified: head/sys/dev/drm/i915_reg.h
==============================================================================
--- head/sys/dev/drm/i915_reg.h Sat Mar 13 11:17:39 2010 (r205119)
+++ head/sys/dev/drm/i915_reg.h Sat Mar 13 11:51:18 2010 (r205120)
@@ -362,6 +362,7 @@ __FBSDID("$FreeBSD$");
#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
+#define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */
#define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
#define I915_CRC_ERROR_ENABLE (1UL<<29)
@@ -438,6 +439,7 @@ __FBSDID("$FreeBSD$");
*/
#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
+#define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15
/* i830, required in DVO non-gang */
#define PLL_P2_DIVIDE_BY_4 (1 << 23)
#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
@@ -504,10 +506,12 @@ __FBSDID("$FreeBSD$");
#define FPB0 0x06048
#define FPB1 0x0604c
#define FP_N_DIV_MASK 0x003f0000
+#define FP_N_IGD_DIV_MASK 0x00ff0000
#define FP_N_DIV_SHIFT 16
#define FP_M1_DIV_MASK 0x00003f00
#define FP_M1_DIV_SHIFT 8
#define FP_M2_DIV_MASK 0x0000003f
+#define FP_M2_IGD_DIV_MASK 0x000000ff
#define FP_M2_DIV_SHIFT 0
#define DPLL_TEST 0x606c
#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
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