svn commit: r212632 - in head/sys/mips: cavium include mips sibyte

[Neel Natu]

Author: neel
Date: Wed Sep 15 05:10:50 2010
New Revision: 212632
URL: http://svn.freebsd.org/changeset/base/212632

Log:
  Make the meaning of the 'mask' argument to 'set_intr_mask(mask)' consistent
  with the meaning of IM bits in the status register.
  
  Reviewed by:  jmallett, jchandra

Modified:
  head/sys/mips/cavium/octeon_mp.c
  head/sys/mips/include/cpufunc.h
  head/sys/mips/mips/machdep.c
  head/sys/mips/mips/trap.c
  head/sys/mips/sibyte/sb_machdep.c

Modified: head/sys/mips/cavium/octeon_mp.c
==============================================================================
--- head/sys/mips/cavium/octeon_mp.c    Wed Sep 15 04:51:07 2010        
(r212631)
+++ head/sys/mips/cavium/octeon_mp.c    Wed Sep 15 05:10:50 2010        
(r212632)
@@ -96,7 +96,7 @@ platform_init_ap(int cpuid)
         */
        clock_int_mask = hard_int_mask(5);
        ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
-       set_intr_mask(MIPS_SR_INT_MASK & ~(ipi_int_mask | clock_int_mask));
+       set_intr_mask(ipi_int_mask | clock_int_mask);
 
        mips_wbflush();
 }

Modified: head/sys/mips/include/cpufunc.h
==============================================================================
--- head/sys/mips/include/cpufunc.h     Wed Sep 15 04:51:07 2010        
(r212631)
+++ head/sys/mips/include/cpufunc.h     Wed Sep 15 05:10:50 2010        
(r212632)
@@ -272,7 +272,7 @@ set_intr_mask(uint32_t mask)
        uint32_t ostatus;
 
        ostatus = mips_rd_status();
-       mask = (ostatus & ~MIPS_SR_INT_MASK) | (~mask & MIPS_SR_INT_MASK);
+       mask = (ostatus & ~MIPS_SR_INT_MASK) | (mask & MIPS_SR_INT_MASK);
        mips_wr_status(mask);
        return (ostatus);
 }

Modified: head/sys/mips/mips/machdep.c
==============================================================================
--- head/sys/mips/mips/machdep.c        Wed Sep 15 04:51:07 2010        
(r212631)
+++ head/sys/mips/mips/machdep.c        Wed Sep 15 05:10:50 2010        
(r212632)
@@ -356,7 +356,7 @@ mips_vector_init(void)
         * Mask all interrupts. Each interrupt will be enabled
         * when handler is installed for it
         */
-       set_intr_mask(MIPS_SR_INT_MASK);
+       set_intr_mask(0);
 
        /* Clear BEV in SR so we start handling our own exceptions */
        mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV);

Modified: head/sys/mips/mips/trap.c
==============================================================================
--- head/sys/mips/mips/trap.c   Wed Sep 15 04:51:07 2010        (r212631)
+++ head/sys/mips/mips/trap.c   Wed Sep 15 05:10:50 2010        (r212632)
@@ -304,7 +304,7 @@ trap(struct trapframe *trapframe)
         * return to userland.
         */
        if (trapframe->sr & MIPS_SR_INT_IE) {
-               set_intr_mask(~(trapframe->sr & MIPS_SR_INT_MASK));
+               set_intr_mask(trapframe->sr & MIPS_SR_INT_MASK);
                intr_enable();
        } else {
                intr_disable();

Modified: head/sys/mips/sibyte/sb_machdep.c
==============================================================================
--- head/sys/mips/sibyte/sb_machdep.c   Wed Sep 15 04:51:07 2010        
(r212631)
+++ head/sys/mips/sibyte/sb_machdep.c   Wed Sep 15 05:10:50 2010        
(r212632)
@@ -370,7 +370,7 @@ platform_init_ap(int cpuid)
         */
        clock_int_mask = hard_int_mask(5);
        ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
-       set_intr_mask(MIPS_SR_INT_MASK & ~(ipi_int_mask | clock_int_mask));
+       set_intr_mask(ipi_int_mask | clock_int_mask);
 }
 
 int
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