Author: yongari
Date: Sat Feb 19 03:23:19 2011
New Revision: 218834
URL: http://svn.freebsd.org/changeset/base/218834
Log:
Consistently use a tab character instead of space after #define.
No functional changes.
Modified:
head/sys/dev/dc/if_dc.c
head/sys/dev/dc/if_dcreg.h
Modified: head/sys/dev/dc/if_dc.c
==============================================================================
--- head/sys/dev/dc/if_dc.c Sat Feb 19 03:01:24 2011 (r218833)
+++ head/sys/dev/dc/if_dc.c Sat Feb 19 03:23:19 2011 (r218834)
@@ -127,7 +127,7 @@ __FBSDID("$FreeBSD$");
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
-#define DC_USEIOSPACE
+#define DC_USEIOSPACE
#include <dev/dc/if_dcreg.h>
@@ -301,11 +301,11 @@ static void dc_apply_fixup(struct dc_sof
static int dc_check_multiport(struct dc_softc *);
#ifdef DC_USEIOSPACE
-#define DC_RES SYS_RES_IOPORT
-#define DC_RID DC_PCI_CFBIO
+#define DC_RES SYS_RES_IOPORT
+#define DC_RID DC_PCI_CFBIO
#else
-#define DC_RES SYS_RES_MEMORY
-#define DC_RID DC_PCI_CFBMA
+#define DC_RES SYS_RES_MEMORY
+#define DC_RID DC_PCI_CFBMA
#endif
static device_method_t dc_methods[] = {
@@ -341,14 +341,14 @@ static devclass_t dc_devclass;
DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0);
DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
-#define DC_SETBIT(sc, reg, x) \
+#define DC_SETBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
-#define DC_CLRBIT(sc, reg, x) \
+#define DC_CLRBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
-#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
-#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
+#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
+#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
static void
dc_delay(struct dc_softc *sc)
@@ -1016,9 +1016,9 @@ dc_miibus_mediainit(device_t dev)
ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
}
-#define DC_BITS_512 9
-#define DC_BITS_128 7
-#define DC_BITS_64 6
+#define DC_BITS_512 9
+#define DC_BITS_128 7
+#define DC_BITS_64 6
static uint32_t
dc_mchash_le(struct dc_softc *sc, const uint8_t *addr)
@@ -2715,7 +2715,7 @@ dc_newbuf(struct dc_softc *sc, int i)
* the time.
*/
-#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG)
+#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG)
static void
dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
{
Modified: head/sys/dev/dc/if_dcreg.h
==============================================================================
--- head/sys/dev/dc/if_dcreg.h Sat Feb 19 03:01:24 2011 (r218833)
+++ head/sys/dev/dc/if_dcreg.h Sat Feb 19 03:23:19 2011 (r218834)
@@ -36,23 +36,23 @@
* 21143 and clone common register definitions.
*/
-#define DC_BUSCTL 0x00 /* bus control */
-#define DC_TXSTART 0x08 /* tx start demand */
-#define DC_RXSTART 0x10 /* rx start demand */
-#define DC_RXADDR 0x18 /* rx descriptor list start addr */
-#define DC_TXADDR 0x20 /* tx descriptor list start addr */
-#define DC_ISR 0x28 /* interrupt status register */
-#define DC_NETCFG 0x30 /* network config register */
-#define DC_IMR 0x38 /* interrupt mask */
-#define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */
-#define DC_SIO 0x48 /* MII and ROM/EEPROM access */
-#define DC_ROM 0x50 /* ROM programming address */
-#define DC_TIMER 0x58 /* general timer */
-#define DC_10BTSTAT 0x60 /* SIA status */
-#define DC_SIARESET 0x68 /* SIA connectivity */
-#define DC_10BTCTRL 0x70 /* SIA transmit and receive */
-#define DC_WATCHDOG 0x78 /* SIA and general purpose port */
-#define DC_SIAGP 0x78 /* SIA and general purpose port (X3201)
*/
+#define DC_BUSCTL 0x00 /* bus control */
+#define DC_TXSTART 0x08 /* tx start demand */
+#define DC_RXSTART 0x10 /* rx start demand */
+#define DC_RXADDR 0x18 /* rx descriptor list start
addr */
+#define DC_TXADDR 0x20 /* tx descriptor list start
addr */
+#define DC_ISR 0x28 /* interrupt status register */
+#define DC_NETCFG 0x30 /* network config register */
+#define DC_IMR 0x38 /* interrupt mask */
+#define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */
+#define DC_SIO 0x48 /* MII and ROM/EEPROM access */
+#define DC_ROM 0x50 /* ROM programming address */
+#define DC_TIMER 0x58 /* general timer */
+#define DC_10BTSTAT 0x60 /* SIA status */
+#define DC_SIARESET 0x68 /* SIA connectivity */
+#define DC_10BTCTRL 0x70 /* SIA transmit and receive */
+#define DC_WATCHDOG 0x78 /* SIA and general purpose port
*/
+#define DC_SIAGP 0x78 /* SIA and general purpose port
(X3201) */
/*
* There are two general 'types' of MX chips that we need to be
@@ -64,328 +64,328 @@
* 'magic' numbers we write to CSR16. The PNIC II falls into the
* 98713A/98715/98715A/98725 category.
*/
-#define DC_TYPE_98713 0x1
-#define DC_TYPE_98713A 0x2
-#define DC_TYPE_987x5 0x3
+#define DC_TYPE_98713 0x1
+#define DC_TYPE_98713A 0x2
+#define DC_TYPE_987x5 0x3
/* Other type of supported chips. */
-#define DC_TYPE_21143 0x4 /* Intel 21143 */
-#define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */
-#define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */
-#define DC_TYPE_AN983 0x7 /* ADMtek AN983 Centaur */
-#define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */
-#define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */
-#define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */
+#define DC_TYPE_21143 0x4 /* Intel 21143 */
+#define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */
+#define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */
+#define DC_TYPE_AN983 0x7 /* ADMtek AN983 Centaur */
+#define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */
+#define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */
+#define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */
#define DC_TYPE_XIRCOM 0xB /* Xircom X3201 */
-#define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */
+#define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */
-#define DC_IS_MACRONIX(x) \
+#define DC_IS_MACRONIX(x) \
(x->dc_type == DC_TYPE_98713 || \
x->dc_type == DC_TYPE_98713A || \
x->dc_type == DC_TYPE_987x5)
-#define DC_IS_ADMTEK(x) \
+#define DC_IS_ADMTEK(x) \
(x->dc_type == DC_TYPE_AL981 || \
x->dc_type == DC_TYPE_AN983)
-#define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143)
-#define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX)
-#define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981)
-#define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN983)
-#define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102)
-#define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII)
-#define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC)
+#define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143)
+#define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX)
+#define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981)
+#define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN983)
+#define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102)
+#define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII)
+#define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC)
#define DC_IS_XIRCOM(x) (x->dc_type == DC_TYPE_XIRCOM)
-#define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT)
+#define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT)
/* MII/symbol mode port types */
-#define DC_PMODE_MII 0x1
-#define DC_PMODE_SYM 0x2
-#define DC_PMODE_SIA 0x3
+#define DC_PMODE_MII 0x1
+#define DC_PMODE_SYM 0x2
+#define DC_PMODE_SIA 0x3
/*
* Bus control bits.
*/
-#define DC_BUSCTL_RESET 0x00000001
-#define DC_BUSCTL_ARBITRATION 0x00000002
-#define DC_BUSCTL_SKIPLEN 0x0000007C
-#define DC_BUSCTL_BUF_BIGENDIAN 0x00000080
-#define DC_BUSCTL_BURSTLEN 0x00003F00
-#define DC_BUSCTL_CACHEALIGN 0x0000C000
-#define DC_BUSCTL_TXPOLL 0x000E0000
-#define DC_BUSCTL_DBO 0x00100000
-#define DC_BUSCTL_MRME 0x00200000
-#define DC_BUSCTL_MRLE 0x00800000
-#define DC_BUSCTL_MWIE 0x01000000
-#define DC_BUSCTL_ONNOW_ENB 0x04000000
-
-#define DC_SKIPLEN_1LONG 0x00000004
-#define DC_SKIPLEN_2LONG 0x00000008
-#define DC_SKIPLEN_3LONG 0x00000010
-#define DC_SKIPLEN_4LONG 0x00000020
-#define DC_SKIPLEN_5LONG 0x00000040
-
-#define DC_CACHEALIGN_NONE 0x00000000
-#define DC_CACHEALIGN_8LONG 0x00004000
-#define DC_CACHEALIGN_16LONG 0x00008000
-#define DC_CACHEALIGN_32LONG 0x0000C000
-
-#define DC_BURSTLEN_USECA 0x00000000
-#define DC_BURSTLEN_1LONG 0x00000100
-#define DC_BURSTLEN_2LONG 0x00000200
-#define DC_BURSTLEN_4LONG 0x00000400
-#define DC_BURSTLEN_8LONG 0x00000800
-#define DC_BURSTLEN_16LONG 0x00001000
-#define DC_BURSTLEN_32LONG 0x00002000
-
-#define DC_TXPOLL_OFF 0x00000000
-#define DC_TXPOLL_1 0x00020000
-#define DC_TXPOLL_2 0x00040000
-#define DC_TXPOLL_3 0x00060000
-#define DC_TXPOLL_4 0x00080000
-#define DC_TXPOLL_5 0x000A0000
-#define DC_TXPOLL_6 0x000C0000
-#define DC_TXPOLL_7 0x000E0000
+#define DC_BUSCTL_RESET 0x00000001
+#define DC_BUSCTL_ARBITRATION 0x00000002
+#define DC_BUSCTL_SKIPLEN 0x0000007C
+#define DC_BUSCTL_BUF_BIGENDIAN 0x00000080
+#define DC_BUSCTL_BURSTLEN 0x00003F00
+#define DC_BUSCTL_CACHEALIGN 0x0000C000
+#define DC_BUSCTL_TXPOLL 0x000E0000
+#define DC_BUSCTL_DBO 0x00100000
+#define DC_BUSCTL_MRME 0x00200000
+#define DC_BUSCTL_MRLE 0x00800000
+#define DC_BUSCTL_MWIE 0x01000000
+#define DC_BUSCTL_ONNOW_ENB 0x04000000
+
+#define DC_SKIPLEN_1LONG 0x00000004
+#define DC_SKIPLEN_2LONG 0x00000008
+#define DC_SKIPLEN_3LONG 0x00000010
+#define DC_SKIPLEN_4LONG 0x00000020
+#define DC_SKIPLEN_5LONG 0x00000040
+
+#define DC_CACHEALIGN_NONE 0x00000000
+#define DC_CACHEALIGN_8LONG 0x00004000
+#define DC_CACHEALIGN_16LONG 0x00008000
+#define DC_CACHEALIGN_32LONG 0x0000C000
+
+#define DC_BURSTLEN_USECA 0x00000000
+#define DC_BURSTLEN_1LONG 0x00000100
+#define DC_BURSTLEN_2LONG 0x00000200
+#define DC_BURSTLEN_4LONG 0x00000400
+#define DC_BURSTLEN_8LONG 0x00000800
+#define DC_BURSTLEN_16LONG 0x00001000
+#define DC_BURSTLEN_32LONG 0x00002000
+
+#define DC_TXPOLL_OFF 0x00000000
+#define DC_TXPOLL_1 0x00020000
+#define DC_TXPOLL_2 0x00040000
+#define DC_TXPOLL_3 0x00060000
+#define DC_TXPOLL_4 0x00080000
+#define DC_TXPOLL_5 0x000A0000
+#define DC_TXPOLL_6 0x000C0000
+#define DC_TXPOLL_7 0x000E0000
/*
* Interrupt status bits.
*/
-#define DC_ISR_TX_OK 0x00000001
-#define DC_ISR_TX_IDLE 0x00000002
-#define DC_ISR_TX_NOBUF 0x00000004
-#define DC_ISR_TX_JABBERTIMEO 0x00000008
-#define DC_ISR_LINKGOOD 0x00000010
-#define DC_ISR_TX_UNDERRUN 0x00000020
-#define DC_ISR_RX_OK 0x00000040
-#define DC_ISR_RX_NOBUF 0x00000080
-#define DC_ISR_RX_READ 0x00000100
-#define DC_ISR_RX_WATDOGTIMEO 0x00000200
-#define DC_ISR_TX_EARLY 0x00000400
-#define DC_ISR_TIMER_EXPIRED 0x00000800
-#define DC_ISR_LINKFAIL 0x00001000
-#define DC_ISR_BUS_ERR 0x00002000
-#define DC_ISR_RX_EARLY 0x00004000
-#define DC_ISR_ABNORMAL 0x00008000
-#define DC_ISR_NORMAL 0x00010000
-#define DC_ISR_RX_STATE 0x000E0000
-#define DC_ISR_TX_STATE 0x00700000
-#define DC_ISR_BUSERRTYPE 0x03800000
-#define DC_ISR_100MBPSLINK 0x08000000
-#define DC_ISR_MAGICKPACK 0x10000000
-
-#define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
-#define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
-#define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
-#define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for
packet */
-#define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
-#define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
-#define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
-#define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
+#define DC_ISR_TX_OK 0x00000001
+#define DC_ISR_TX_IDLE 0x00000002
+#define DC_ISR_TX_NOBUF 0x00000004
+#define DC_ISR_TX_JABBERTIMEO 0x00000008
+#define DC_ISR_LINKGOOD 0x00000010
+#define DC_ISR_TX_UNDERRUN 0x00000020
+#define DC_ISR_RX_OK 0x00000040
+#define DC_ISR_RX_NOBUF 0x00000080
+#define DC_ISR_RX_READ 0x00000100
+#define DC_ISR_RX_WATDOGTIMEO 0x00000200
+#define DC_ISR_TX_EARLY 0x00000400
+#define DC_ISR_TIMER_EXPIRED 0x00000800
+#define DC_ISR_LINKFAIL 0x00001000
+#define DC_ISR_BUS_ERR 0x00002000
+#define DC_ISR_RX_EARLY 0x00004000
+#define DC_ISR_ABNORMAL 0x00008000
+#define DC_ISR_NORMAL 0x00010000
+#define DC_ISR_RX_STATE 0x000E0000
+#define DC_ISR_TX_STATE 0x00700000
+#define DC_ISR_BUSERRTYPE 0x03800000
+#define DC_ISR_100MBPSLINK 0x08000000
+#define DC_ISR_MAGICKPACK 0x10000000
+
+#define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
+#define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching
descriptor */
+#define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx
end */
+#define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for
packet */
+#define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
+#define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc
*/
+#define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from
FIFO */
+#define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from
FIFO */
#define DC_HAS_BROKEN_RXSTATE(x)
\
(DC_IS_CENTAUR(x) || DC_IS_CONEXANT(x) || (DC_IS_DAVICOM(x) && \
pci_get_revid((x)->dc_dev) >= DC_REVISION_DM9102A))
-#define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */
-#define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
-#define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
-#define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
-#define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
-#define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
-#define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
-#define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
+#define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */
+#define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching
descriptor */
+#define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx
end */
+#define DC_TXSTATE_READING 0x00300000 /* 011 - read and
enqueue */
+#define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
+#define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
+#define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
+#define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc
*/
/*
* Network config bits.
*/
-#define DC_NETCFG_RX_HASHPERF 0x00000001
-#define DC_NETCFG_RX_ON 0x00000002
-#define DC_NETCFG_RX_HASHONLY 0x00000004
-#define DC_NETCFG_RX_BADFRAMES 0x00000008
-#define DC_NETCFG_RX_INVFILT 0x00000010
-#define DC_NETCFG_BACKOFFCNT 0x00000020
-#define DC_NETCFG_RX_PROMISC 0x00000040
-#define DC_NETCFG_RX_ALLMULTI 0x00000080
-#define DC_NETCFG_FULLDUPLEX 0x00000200
-#define DC_NETCFG_LOOPBACK 0x00000C00
-#define DC_NETCFG_FORCECOLL 0x00001000
-#define DC_NETCFG_TX_ON 0x00002000
-#define DC_NETCFG_TX_THRESH 0x0000C000
-#define DC_NETCFG_TX_BACKOFF 0x00020000
-#define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */
-#define DC_NETCFG_HEARTBEAT 0x00080000
-#define DC_NETCFG_STORENFWD 0x00200000
-#define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */
-#define DC_NETCFG_PCS 0x00800000
-#define DC_NETCFG_SCRAMBLER 0x01000000
-#define DC_NETCFG_NO_RXCRC 0x02000000
-#define DC_NETCFG_RX_ALL 0x40000000
-#define DC_NETCFG_CAPEFFECT 0x80000000
-
-#define DC_OPMODE_NORM 0x00000000
-#define DC_OPMODE_INTLOOP 0x00000400
-#define DC_OPMODE_EXTLOOP 0x00000800
+#define DC_NETCFG_RX_HASHPERF 0x00000001
+#define DC_NETCFG_RX_ON 0x00000002
+#define DC_NETCFG_RX_HASHONLY 0x00000004
+#define DC_NETCFG_RX_BADFRAMES 0x00000008
+#define DC_NETCFG_RX_INVFILT 0x00000010
+#define DC_NETCFG_BACKOFFCNT 0x00000020
+#define DC_NETCFG_RX_PROMISC 0x00000040
+#define DC_NETCFG_RX_ALLMULTI 0x00000080
+#define DC_NETCFG_FULLDUPLEX 0x00000200
+#define DC_NETCFG_LOOPBACK 0x00000C00
+#define DC_NETCFG_FORCECOLL 0x00001000
+#define DC_NETCFG_TX_ON 0x00002000
+#define DC_NETCFG_TX_THRESH 0x0000C000
+#define DC_NETCFG_TX_BACKOFF 0x00020000
+#define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */
+#define DC_NETCFG_HEARTBEAT 0x00080000
+#define DC_NETCFG_STORENFWD 0x00200000
+#define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */
+#define DC_NETCFG_PCS 0x00800000
+#define DC_NETCFG_SCRAMBLER 0x01000000
+#define DC_NETCFG_NO_RXCRC 0x02000000
+#define DC_NETCFG_RX_ALL 0x40000000
+#define DC_NETCFG_CAPEFFECT 0x80000000
+
+#define DC_OPMODE_NORM 0x00000000
+#define DC_OPMODE_INTLOOP 0x00000400
+#define DC_OPMODE_EXTLOOP 0x00000800
#if 0
-#define DC_TXTHRESH_72BYTES 0x00000000
-#define DC_TXTHRESH_96BYTES 0x00004000
-#define DC_TXTHRESH_128BYTES 0x00008000
-#define DC_TXTHRESH_160BYTES 0x0000C000
+#define DC_TXTHRESH_72BYTES 0x00000000
+#define DC_TXTHRESH_96BYTES 0x00004000
+#define DC_TXTHRESH_128BYTES 0x00008000
+#define DC_TXTHRESH_160BYTES 0x0000C000
#endif
-#define DC_TXTHRESH_MIN 0x00000000
-#define DC_TXTHRESH_INC 0x00004000
-#define DC_TXTHRESH_MAX 0x0000C000
+#define DC_TXTHRESH_MIN 0x00000000
+#define DC_TXTHRESH_INC 0x00004000
+#define DC_TXTHRESH_MAX 0x0000C000
/*
* Interrupt mask bits.
*/
-#define DC_IMR_TX_OK 0x00000001
-#define DC_IMR_TX_IDLE 0x00000002
-#define DC_IMR_TX_NOBUF 0x00000004
-#define DC_IMR_TX_JABBERTIMEO 0x00000008
-#define DC_IMR_LINKGOOD 0x00000010
-#define DC_IMR_TX_UNDERRUN 0x00000020
-#define DC_IMR_RX_OK 0x00000040
-#define DC_IMR_RX_NOBUF 0x00000080
-#define DC_IMR_RX_READ 0x00000100
-#define DC_IMR_RX_WATDOGTIMEO 0x00000200
-#define DC_IMR_TX_EARLY 0x00000400
-#define DC_IMR_TIMER_EXPIRED 0x00000800
-#define DC_IMR_LINKFAIL 0x00001000
-#define DC_IMR_BUS_ERR 0x00002000
-#define DC_IMR_RX_EARLY 0x00004000
-#define DC_IMR_ABNORMAL 0x00008000
-#define DC_IMR_NORMAL 0x00010000
-#define DC_IMR_100MBPSLINK 0x08000000
-#define DC_IMR_MAGICKPACK 0x10000000
+#define DC_IMR_TX_OK 0x00000001
+#define DC_IMR_TX_IDLE 0x00000002
+#define DC_IMR_TX_NOBUF 0x00000004
+#define DC_IMR_TX_JABBERTIMEO 0x00000008
+#define DC_IMR_LINKGOOD 0x00000010
+#define DC_IMR_TX_UNDERRUN 0x00000020
+#define DC_IMR_RX_OK 0x00000040
+#define DC_IMR_RX_NOBUF 0x00000080
+#define DC_IMR_RX_READ 0x00000100
+#define DC_IMR_RX_WATDOGTIMEO 0x00000200
+#define DC_IMR_TX_EARLY 0x00000400
+#define DC_IMR_TIMER_EXPIRED 0x00000800
+#define DC_IMR_LINKFAIL 0x00001000
+#define DC_IMR_BUS_ERR 0x00002000
+#define DC_IMR_RX_EARLY 0x00004000
+#define DC_IMR_ABNORMAL 0x00008000
+#define DC_IMR_NORMAL 0x00010000
+#define DC_IMR_100MBPSLINK 0x08000000
+#define DC_IMR_MAGICKPACK 0x10000000
-#define DC_INTRS \
+#define DC_INTRS \
(DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\
DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \
DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/)
/*
* Serial I/O (EEPROM/ROM) bits.
*/
-#define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */
-#define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */
-#define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
-#define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
-#define DC_SIO_ROMDATA4 0x00000010
-#define DC_SIO_ROMDATA5 0x00000020
-#define DC_SIO_ROMDATA6 0x00000040
-#define DC_SIO_ROMDATA7 0x00000080
-#define DC_SIO_EESEL 0x00000800
-#define DC_SIO_ROMSEL 0x00001000
-#define DC_SIO_ROMCTL_WRITE 0x00002000
-#define DC_SIO_ROMCTL_READ 0x00004000
-#define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */
-#define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
-#define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */
-#define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
-
-#define DC_EECMD_WRITE 0x140
-#define DC_EECMD_READ 0x180
-#define DC_EECMD_ERASE 0x1c0
+#define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */
+#define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */
+#define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
+#define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
+#define DC_SIO_ROMDATA4 0x00000010
+#define DC_SIO_ROMDATA5 0x00000020
+#define DC_SIO_ROMDATA6 0x00000040
+#define DC_SIO_ROMDATA7 0x00000080
+#define DC_SIO_EESEL 0x00000800
+#define DC_SIO_ROMSEL 0x00001000
+#define DC_SIO_ROMCTL_WRITE 0x00002000
+#define DC_SIO_ROMCTL_READ 0x00004000
+#define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */
+#define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
+#define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */
+#define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
+
+#define DC_EECMD_WRITE 0x140
+#define DC_EECMD_READ 0x180
+#define DC_EECMD_ERASE 0x1c0
-#define DC_EE_NODEADDR_OFFSET 0x70
-#define DC_EE_NODEADDR 10
+#define DC_EE_NODEADDR_OFFSET 0x70
+#define DC_EE_NODEADDR 10
/*
* General purpose timer register
*/
-#define DC_TIMER_VALUE 0x0000FFFF
-#define DC_TIMER_CONTINUOUS 0x00010000
+#define DC_TIMER_VALUE 0x0000FFFF
+#define DC_TIMER_CONTINUOUS 0x00010000
/*
* 10baseT status register
*/
-#define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */
-#define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */
-#define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */
-#define DC_TSTAT_AUTOPOLARITY 0x00000008
-#define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */
-#define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */
-#define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */
-#define DC_TSTAT_REMFAULT 0x00000800
-#define DC_TSTAT_ANEGSTAT 0x00007000
-#define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */
-#define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */
-
-#define DC_ASTAT_DISABLE 0x00000000
-#define DC_ASTAT_TXDISABLE 0x00001000
-#define DC_ASTAT_ABDETECT 0x00002000
-#define DC_ASTAT_ACKDETECT 0x00003000
-#define DC_ASTAT_CMPACKDETECT 0x00004000
-#define DC_ASTAT_AUTONEGCMP 0x00005000
-#define DC_ASTAT_LINKCHECK 0x00006000
+#define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */
+#define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX
*/
+#define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */
+#define DC_TSTAT_AUTOPOLARITY 0x00000008
+#define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */
+#define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */
+#define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected
*/
+#define DC_TSTAT_REMFAULT 0x00000800
+#define DC_TSTAT_ANEGSTAT 0x00007000
+#define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports
NWAY */
+#define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word
*/
+
+#define DC_ASTAT_DISABLE 0x00000000
+#define DC_ASTAT_TXDISABLE 0x00001000
+#define DC_ASTAT_ABDETECT 0x00002000
+#define DC_ASTAT_ACKDETECT 0x00003000
+#define DC_ASTAT_CMPACKDETECT 0x00004000
+#define DC_ASTAT_AUTONEGCMP 0x00005000
+#define DC_ASTAT_LINKCHECK 0x00006000
/*
* PHY reset register
*/
-#define DC_SIA_RESET 0x00000001
-#define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */
+#define DC_SIA_RESET 0x00000001
+#define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */
/*
* 10baseT control register
*/
-#define DC_TCTL_ENCODER_ENB 0x00000001
-#define DC_TCTL_LOOPBACK 0x00000002
-#define DC_TCTL_DRIVER_ENB 0x00000004
-#define DC_TCTL_LNKPULSE_ENB 0x00000008
-#define DC_TCTL_HALFDUPLEX 0x00000040
-#define DC_TCTL_AUTONEGENBL 0x00000080
-#define DC_TCTL_RX_SQUELCH 0x00000100
-#define DC_TCTL_COLL_SQUELCH 0x00000200
-#define DC_TCTL_COLL_DETECT 0x00000400
-#define DC_TCTL_SQE_ENB 0x00000800
-#define DC_TCTL_LINKTEST 0x00001000
-#define DC_TCTL_AUTOPOLARITY 0x00002000
-#define DC_TCTL_SET_POL_PLUS 0x00004000
-#define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */
-#define DC_TCTL_100BTXHALF 0x00010000
-#define DC_TCTL_100BTXFULL 0x00020000
-#define DC_TCTL_100BT4 0x00040000
+#define DC_TCTL_ENCODER_ENB 0x00000001
+#define DC_TCTL_LOOPBACK 0x00000002
+#define DC_TCTL_DRIVER_ENB 0x00000004
+#define DC_TCTL_LNKPULSE_ENB 0x00000008
+#define DC_TCTL_HALFDUPLEX 0x00000040
+#define DC_TCTL_AUTONEGENBL 0x00000080
+#define DC_TCTL_RX_SQUELCH 0x00000100
+#define DC_TCTL_COLL_SQUELCH 0x00000200
+#define DC_TCTL_COLL_DETECT 0x00000400
+#define DC_TCTL_SQE_ENB 0x00000800
+#define DC_TCTL_LINKTEST 0x00001000
+#define DC_TCTL_AUTOPOLARITY 0x00002000
+#define DC_TCTL_SET_POL_PLUS 0x00004000
+#define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */
+#define DC_TCTL_100BTXHALF 0x00010000
+#define DC_TCTL_100BTXFULL 0x00020000
+#define DC_TCTL_100BT4 0x00040000
/*
* Watchdog timer register
*/
-#define DC_WDOG_JABBERDIS 0x00000001
-#define DC_WDOG_HOSTUNJAB 0x00000002
-#define DC_WDOG_JABBERCLK 0x00000004
-#define DC_WDOG_RXWDOGDIS 0x00000010
-#define DC_WDOG_RXWDOGCLK 0x00000020
-#define DC_WDOG_MUSTBEZERO 0x00000100
-#define DC_WDOG_AUIBNC 0x00100000
-#define DC_WDOG_ACTIVITY 0x00200000
-#define DC_WDOG_RX_MATCH 0x00400000
-#define DC_WDOG_LINK 0x00800000
-#define DC_WDOG_CTLWREN 0x08000000
+#define DC_WDOG_JABBERDIS 0x00000001
+#define DC_WDOG_HOSTUNJAB 0x00000002
+#define DC_WDOG_JABBERCLK 0x00000004
+#define DC_WDOG_RXWDOGDIS 0x00000010
+#define DC_WDOG_RXWDOGCLK 0x00000020
+#define DC_WDOG_MUSTBEZERO 0x00000100
+#define DC_WDOG_AUIBNC 0x00100000
+#define DC_WDOG_ACTIVITY 0x00200000
+#define DC_WDOG_RX_MATCH 0x00400000
+#define DC_WDOG_LINK 0x00800000
+#define DC_WDOG_CTLWREN 0x08000000
/*
* SIA and General Purpose Port register (X3201)
*/
-#define DC_SIAGP_RXMATCH 0x40000000
-#define DC_SIAGP_INT1 0x20000000
-#define DC_SIAGP_INT0 0x10000000
-#define DC_SIAGP_WRITE_EN 0x08000000
-#define DC_SIAGP_RXMATCH_EN 0x04000000
-#define DC_SIAGP_INT1_EN 0x02000000
-#define DC_SIAGP_INT0_EN 0x01000000
-#define DC_SIAGP_LED3 0x00800000
-#define DC_SIAGP_LED2 0x00400000
-#define DC_SIAGP_LED1 0x00200000
-#define DC_SIAGP_LED0 0x00100000
-#define DC_SIAGP_MD_GP3_OUTPUT 0x00080000
-#define DC_SIAGP_MD_GP2_OUTPUT 0x00040000
-#define DC_SIAGP_MD_GP1_OUTPUT 0x00020000
-#define DC_SIAGP_MD_GP0_OUTPUT 0x00010000
+#define DC_SIAGP_RXMATCH 0x40000000
+#define DC_SIAGP_INT1 0x20000000
+#define DC_SIAGP_INT0 0x10000000
+#define DC_SIAGP_WRITE_EN 0x08000000
+#define DC_SIAGP_RXMATCH_EN 0x04000000
+#define DC_SIAGP_INT1_EN 0x02000000
+#define DC_SIAGP_INT0_EN 0x01000000
+#define DC_SIAGP_LED3 0x00800000
+#define DC_SIAGP_LED2 0x00400000
+#define DC_SIAGP_LED1 0x00200000
+#define DC_SIAGP_LED0 0x00100000
+#define DC_SIAGP_MD_GP3_OUTPUT 0x00080000
+#define DC_SIAGP_MD_GP2_OUTPUT 0x00040000
+#define DC_SIAGP_MD_GP1_OUTPUT 0x00020000
+#define DC_SIAGP_MD_GP0_OUTPUT 0x00010000
/*
* Size of a setup frame.
*/
-#define DC_SFRAME_LEN 192
+#define DC_SFRAME_LEN 192
/*
* 21x4x TX/RX list structure.
@@ -398,93 +398,93 @@ struct dc_desc {
u_int32_t dc_ptr2;
};
-#define dc_data dc_ptr1
-#define dc_next dc_ptr2
+#define dc_data dc_ptr1
+#define dc_next dc_ptr2
-#define DC_RXSTAT_FIFOOFLOW 0x00000001
-#define DC_RXSTAT_CRCERR 0x00000002
-#define DC_RXSTAT_DRIBBLE 0x00000004
-#define DC_RXSTAT_MIIERE 0x00000008
-#define DC_RXSTAT_WATCHDOG 0x00000010
-#define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
-#define DC_RXSTAT_COLLSEEN 0x00000040
-#define DC_RXSTAT_GIANT 0x00000080
-#define DC_RXSTAT_LASTFRAG 0x00000100
-#define DC_RXSTAT_FIRSTFRAG 0x00000200
-#define DC_RXSTAT_MULTICAST 0x00000400
-#define DC_RXSTAT_RUNT 0x00000800
-#define DC_RXSTAT_RXTYPE 0x00003000
-#define DC_RXSTAT_DE 0x00004000
-#define DC_RXSTAT_RXERR 0x00008000
-#define DC_RXSTAT_RXLEN 0x3FFF0000
-#define DC_RXSTAT_OWN 0x80000000
-
-#define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16)
-#define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN)
-
-#define DC_RXCTL_BUFLEN1 0x00000FFF
-#define DC_RXCTL_BUFLEN2 0x00FFF000
-#define DC_RXCTL_RLINK 0x01000000
-#define DC_RXCTL_RLAST 0x02000000
-
-#define DC_TXSTAT_DEFER 0x00000001
-#define DC_TXSTAT_UNDERRUN 0x00000002
-#define DC_TXSTAT_LINKFAIL 0x00000003
-#define DC_TXSTAT_COLLCNT 0x00000078
-#define DC_TXSTAT_SQE 0x00000080
-#define DC_TXSTAT_EXCESSCOLL 0x00000100
-#define DC_TXSTAT_LATECOLL 0x00000200
-#define DC_TXSTAT_NOCARRIER 0x00000400
-#define DC_TXSTAT_CARRLOST 0x00000800
-#define DC_TXSTAT_JABTIMEO 0x00004000
-#define DC_TXSTAT_ERRSUM 0x00008000
-#define DC_TXSTAT_OWN 0x80000000
-
-#define DC_TXCTL_BUFLEN1 0x000007FF
-#define DC_TXCTL_BUFLEN2 0x003FF800
-#define DC_TXCTL_FILTTYPE0 0x00400000
-#define DC_TXCTL_PAD 0x00800000
-#define DC_TXCTL_TLINK 0x01000000
-#define DC_TXCTL_TLAST 0x02000000
-#define DC_TXCTL_NOCRC 0x04000000
-#define DC_TXCTL_SETUP 0x08000000
-#define DC_TXCTL_FILTTYPE1 0x10000000
-#define DC_TXCTL_FIRSTFRAG 0x20000000
-#define DC_TXCTL_LASTFRAG 0x40000000
-#define DC_TXCTL_FINT 0x80000000
-
-#define DC_FILTER_PERFECT 0x00000000
-#define DC_FILTER_HASHPERF 0x00400000
-#define DC_FILTER_INVERSE 0x10000000
-#define DC_FILTER_HASHONLY 0x10400000
+#define DC_RXSTAT_FIFOOFLOW 0x00000001
+#define DC_RXSTAT_CRCERR 0x00000002
+#define DC_RXSTAT_DRIBBLE 0x00000004
+#define DC_RXSTAT_MIIERE 0x00000008
+#define DC_RXSTAT_WATCHDOG 0x00000010
+#define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
+#define DC_RXSTAT_COLLSEEN 0x00000040
+#define DC_RXSTAT_GIANT 0x00000080
+#define DC_RXSTAT_LASTFRAG 0x00000100
+#define DC_RXSTAT_FIRSTFRAG 0x00000200
+#define DC_RXSTAT_MULTICAST 0x00000400
+#define DC_RXSTAT_RUNT 0x00000800
+#define DC_RXSTAT_RXTYPE 0x00003000
+#define DC_RXSTAT_DE 0x00004000
+#define DC_RXSTAT_RXERR 0x00008000
+#define DC_RXSTAT_RXLEN 0x3FFF0000
+#define DC_RXSTAT_OWN 0x80000000
+
+#define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16)
+#define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN)
+
+#define DC_RXCTL_BUFLEN1 0x00000FFF
+#define DC_RXCTL_BUFLEN2 0x00FFF000
+#define DC_RXCTL_RLINK 0x01000000
+#define DC_RXCTL_RLAST 0x02000000
+
+#define DC_TXSTAT_DEFER 0x00000001
+#define DC_TXSTAT_UNDERRUN 0x00000002
+#define DC_TXSTAT_LINKFAIL 0x00000003
+#define DC_TXSTAT_COLLCNT 0x00000078
+#define DC_TXSTAT_SQE 0x00000080
+#define DC_TXSTAT_EXCESSCOLL 0x00000100
+#define DC_TXSTAT_LATECOLL 0x00000200
+#define DC_TXSTAT_NOCARRIER 0x00000400
+#define DC_TXSTAT_CARRLOST 0x00000800
+#define DC_TXSTAT_JABTIMEO 0x00004000
+#define DC_TXSTAT_ERRSUM 0x00008000
+#define DC_TXSTAT_OWN 0x80000000
+
+#define DC_TXCTL_BUFLEN1 0x000007FF
+#define DC_TXCTL_BUFLEN2 0x003FF800
+#define DC_TXCTL_FILTTYPE0 0x00400000
+#define DC_TXCTL_PAD 0x00800000
+#define DC_TXCTL_TLINK 0x01000000
+#define DC_TXCTL_TLAST 0x02000000
+#define DC_TXCTL_NOCRC 0x04000000
+#define DC_TXCTL_SETUP 0x08000000
+#define DC_TXCTL_FILTTYPE1 0x10000000
+#define DC_TXCTL_FIRSTFRAG 0x20000000
+#define DC_TXCTL_LASTFRAG 0x40000000
+#define DC_TXCTL_FINT 0x80000000
+
+#define DC_FILTER_PERFECT 0x00000000
+#define DC_FILTER_HASHPERF 0x00400000
+#define DC_FILTER_INVERSE 0x10000000
+#define DC_FILTER_HASHONLY 0x10400000
-#define DC_MAXFRAGS 16
+#define DC_MAXFRAGS 16
#ifdef DEVICE_POLLING
-#define DC_RX_LIST_CNT 192
+#define DC_RX_LIST_CNT 192
#else
-#define DC_RX_LIST_CNT 64
+#define DC_RX_LIST_CNT 64
#endif
-#define DC_TX_LIST_CNT 256
-#define DC_TX_LIST_RSVD 5
-#define DC_MIN_FRAMELEN 60
-#define DC_RXLEN 1536
+#define DC_TX_LIST_CNT 256
+#define DC_TX_LIST_RSVD 5
+#define DC_MIN_FRAMELEN 60
+#define DC_RXLEN 1536
-#define DC_INC(x, y) (x) = (x + 1) % y
+#define DC_INC(x, y) (x) = (x + 1) % y
#define DC_LIST_ALIGN (sizeof(struct dc_desc))
#define DC_RXBUF_ALIGN 4
/* Macros to easily get the DMA address of a descriptor. */
#define DC_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF)
-#define DC_RXDESC(sc, i) \
+#define DC_RXDESC(sc, i) \
(DC_ADDR_LO(sc->dc_ldata.dc_rx_list_paddr + (sizeof(struct dc_desc) * i)))
-#define DC_TXDESC(sc, i) \
+#define DC_TXDESC(sc, i) \
(DC_ADDR_LO(sc->dc_ldata.dc_tx_list_paddr + (sizeof(struct dc_desc) * i)))
#if BYTE_ORDER == BIG_ENDIAN
-#define DC_SP_MAC(x) ((x) << 16)
+#define DC_SP_MAC(x) ((x) << 16)
#else
-#define DC_SP_MAC(x) (x)
+#define DC_SP_MAC(x) (x)
#endif
struct dc_list_data {
@@ -540,10 +540,10 @@ struct dc_mii_frame {
/*
* MII constants
*/
-#define DC_MII_STARTDELIM 0x01
-#define DC_MII_READOP 0x02
-#define DC_MII_WRITEOP 0x01
-#define DC_MII_TURNAROUND 0x02
+#define DC_MII_STARTDELIM 0x01
+#define DC_MII_READOP 0x02
+#define DC_MII_WRITEOP 0x01
+#define DC_MII_TURNAROUND 0x02
/*
@@ -556,42 +556,42 @@ struct dc_mii_frame {
* ADMtek specific registers and constants for the AL981 and AN983.
* The AN983 doesn't use the magic PHY registers.
*/
-#define DC_AL_CR 0x88 /* command register */
-#define DC_AL_PAR0 0xA4 /* station address */
-#define DC_AL_PAR1 0xA8 /* station address */
-#define DC_AL_MAR0 0xAC /* multicast hash filter */
-#define DC_AL_MAR1 0xB0 /* multicast hash filter */
-#define DC_AL_BMCR 0xB4 /* built in PHY control */
-#define DC_AL_BMSR 0xB8 /* built in PHY status */
-#define DC_AL_VENID 0xBC /* built in PHY ID0 */
-#define DC_AL_DEVID 0xC0 /* built in PHY ID1 */
-#define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */
-#define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */
-#define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */
-
-#define DC_AL_CR_ATUR 0x00000001 /* automatic TX underrun recovery */
-#define DC_ADMTEK_PHYADDR 0x1
-#define DC_AL_EE_NODEADDR 4
+#define DC_AL_CR 0x88 /* command register */
+#define DC_AL_PAR0 0xA4 /* station address */
+#define DC_AL_PAR1 0xA8 /* station address */
+#define DC_AL_MAR0 0xAC /* multicast hash filter */
+#define DC_AL_MAR1 0xB0 /* multicast hash filter */
+#define DC_AL_BMCR 0xB4 /* built in PHY control */
+#define DC_AL_BMSR 0xB8 /* built in PHY status */
+#define DC_AL_VENID 0xBC /* built in PHY ID0 */
+#define DC_AL_DEVID 0xC0 /* built in PHY ID1 */
+#define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert
*/
+#define DC_AL_LPAR 0xC8 /* bnilt in PHY link part.
ability */
+#define DC_AL_ANER 0xCC /* built in PHY autoneg
expansion */
+
+#define DC_AL_CR_ATUR 0x00000001 /* automatic TX underrun
recovery */
+#define DC_ADMTEK_PHYADDR 0x1
+#define DC_AL_EE_NODEADDR 4
/* End of ADMtek specific registers */
/*
* ASIX specific registers.
*/
-#define DC_AX_FILTIDX 0x68 /* RX filter index */
-#define DC_AX_FILTDATA 0x70 /* RX filter data */
+#define DC_AX_FILTIDX 0x68 /* RX filter index */
+#define DC_AX_FILTDATA 0x70 /* RX filter data */
/*
* Special ASIX-specific bits in the ASIX NETCFG register (CSR6).
*/
-#define DC_AX_NETCFG_RX_BROAD 0x00000100
+#define DC_AX_NETCFG_RX_BROAD 0x00000100
/*
* RX Filter Index Register values
*/
-#define DC_AX_FILTIDX_PAR0 0x00000000
-#define DC_AX_FILTIDX_PAR1 0x00000001
-#define DC_AX_FILTIDX_MAR0 0x00000002
-#define DC_AX_FILTIDX_MAR1 0x00000003
+#define DC_AX_FILTIDX_PAR0 0x00000000
+#define DC_AX_FILTIDX_PAR1 0x00000001
+#define DC_AX_FILTIDX_MAR0 0x00000002
+#define DC_AX_FILTIDX_MAR1 0x00000003
/* End of ASIX specific registers */
/*
@@ -600,22 +600,22 @@ struct dc_mii_frame {
* a magic packet register, which we need to tweak a bit per the
* Macronix application notes.
*/
-#define DC_MX_MAGICPACKET 0x80
-#define DC_MX_NWAYSTAT 0xA0
+#define DC_MX_MAGICPACKET 0x80
+#define DC_MX_NWAYSTAT 0xA0
/*
* Magic packet register
*/
-#define DC_MX_MPACK_DISABLE 0x00400000
+#define DC_MX_MPACK_DISABLE 0x00400000
/*
* NWAY status register.
*/
-#define DC_MX_NWAY_10BTHALF 0x08000000
-#define DC_MX_NWAY_10BTFULL 0x10000000
-#define DC_MX_NWAY_100BTHALF 0x20000000
-#define DC_MX_NWAY_100BTFULL 0x40000000
-#define DC_MX_NWAY_100BT4 0x80000000
+#define DC_MX_NWAY_10BTHALF 0x08000000
+#define DC_MX_NWAY_10BTFULL 0x10000000
+#define DC_MX_NWAY_100BTHALF 0x20000000
+#define DC_MX_NWAY_100BTFULL 0x40000000
+#define DC_MX_NWAY_100BT4 0x80000000
/*
* These are magic values that must be written into CSR16
@@ -623,10 +623,10 @@ struct dc_mii_frame {
* operating mode. The magic numbers are documented in the
* Macronix 98715 application notes.
*/
-#define DC_MX_MAGIC_98713 0x0F370000
-#define DC_MX_MAGIC_98713A 0x0B3C0000
-#define DC_MX_MAGIC_98715 0x0B3C0000
-#define DC_MX_MAGIC_98725 0x0B3C0000
+#define DC_MX_MAGIC_98713 0x0F370000
+#define DC_MX_MAGIC_98713A 0x0B3C0000
+#define DC_MX_MAGIC_98715 0x0B3C0000
+#define DC_MX_MAGIC_98725 0x0B3C0000
/* End of Macronix specific registers */
/*
@@ -634,20 +634,20 @@ struct dc_mii_frame {
* The PNIC has its own special NWAY support, which doesn't work,
* and shortcut ways of reading the EEPROM and MII bus.
*/
-#define DC_PN_GPIO 0x60 /* general purpose pins control */
-#define DC_PN_PWRUP_CFG 0x90 /* config register, set by
EEPROM */
-#define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */
-#define DC_PN_MII 0xA0 /* MII access register */
-#define DC_PN_NWAY 0xB8 /* Internal NWAY register */
+#define DC_PN_GPIO 0x60 /* general purpose pins control
*/
+#define DC_PN_PWRUP_CFG 0x90 /* config register, set by
EEPROM */
+#define DC_PN_SIOCTL 0x98 /* serial EEPROM control
register */
+#define DC_PN_MII 0xA0 /* MII access register */
+#define DC_PN_NWAY 0xB8 /* Internal NWAY register */
/* Serial I/O EEPROM register */
-#define DC_PN_SIOCTL_DATA 0x0000003F
-#define DC_PN_SIOCTL_OPCODE 0x00000300
-#define DC_PN_SIOCTL_BUSY 0x80000000
-
-#define DC_PN_EEOPCODE_ERASE 0x00000300
-#define DC_PN_EEOPCODE_READ 0x00000600
-#define DC_PN_EEOPCODE_WRITE 0x00000100
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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